See the Typical Performance Characteristics section for more information.
With all digital inputs forced to VDD or GND, as required.
3
During acquisition phase.
Rev. 0 | Page 3 of 16
AD7684
VDD = 5 V; V
REF
= VDD; T
A
= –40°C to +85°C, unless otherwise noted.
Table 3.
Parameter
ACCURACY
No Missing Codes
Integral Linearity Error
Transition Noise
Gain Error
1
, T
MIN
to T
MAX
Gain Error Temperature Drift
Zero Error , T
MIN
to T
MAX
Zero Temperature Drift
Power Supply Sensitivity
1
Conditions
Min
16
−3
Typ
Max
Unit
Bits
LSB
LSB
LSB
ppm/°C
mV
ppm/°C
LSB
dB
2
dB
dB
dB
Bits
VDD = 5 V
±5%
f
IN
= 1 kHz
f
IN
= 1 kHz
f
IN
= 1 kHz
f
IN
= 1 kHz
f
IN
= 1 kHz
88
±1
0.5
±2
±0.3
±0.4
±0.3
±0.05
91
−108
−106
91
14.8
+3
±15
±1.6
AC ACCURACY
Signal-to-Noise
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
Effective Number of Bits
88
1
2
See the Terminology section. These specifications include full temperature range variation, but do not include the error contribution from the external reference.
All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
VDD = 2.7 V; V
REF
= 2.5 V; T
A
= –40°C to +85°C, unless otherwise noted.
Table 4.
Parameter
ACCURACY
No Missing Codes
Integral Linearity Error
Transition Noise
Gain Error
1
, T
MIN
to T
MAX
Gain Error Temperature Drift
Zero Error , T
MIN
to T
MAX
Zero Temperature Drift
Power Supply Sensitivity
1
Conditions
Min
16
−3
Typ
Max
Unit
Bits
LSB
LSB
LSB
ppm/°C
mV
ppm/°C
LSB
dB
2
dB
dB
dB
Bits
VDD = 2.7 V
±5%
f
IN
= 1 kHz
f
IN
= 1 kHz
f
IN
= 1 kHz
f
IN
= 1 kHz
f
IN
= 1 kHz
±1
0.85
±2
±0.3
±0.7
±0.3
±0.05
86
−100
−98
86
14
+3
±15
±3.5
AC ACCURACY
Signal-to-Noise
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
Effective Number of Bits
1
2
See the Terminology section. These specifications do include full temperature range variation, but do not include the error contribution from the external reference.
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
Rev. 0 | Page 4 of 16
AD7684
TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; T
A
= −40°C to +85°C, unless otherwise noted.
Table 5.
Parameter
Throughput Rate
CS Falling to DCLOCK Low
CS Falling to DCLOCK Rising
DCLOCK Falling to Data Remains Valid
CS Rising Edge to D
OUT
High Impedance
DCLOCK Falling to Data Valid
Acquisition Time
D
OUT
Fall Time
D
OUT
Rise Time
Symbol
t
CYC
t
CSD
t
SUCS
t
HDO
t
DIS
t
EN
t
ACQ
t
F
t
R
Min
Typ
Max
100
0
Unit
kHz
µs
ns
ns
ns
ns
ns
ns
ns
20
5
16
14
16
11
11
100
50
25
25
400
t
CYC
CS
COMPLETE CYCLE
t
SUCS
POWER DOWN
DCLOCK
1
4
5
t
ACQ
t
CSD
D
OUT
Hi-Z
0
t
EN
t
HDO
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
t
DIS
Hi-Z
D15 D14 D13 D12 D11 D10 D9
Figure 2. Serial Interface Timing
Rev. 0 | Page 5 of 16
04302-002
(MSB)
(LSB)
NOTE:
A MINIMUM OF 22 CLOCK CYCLES ARE REQUIRED FOR 16-BIT CONVERSION. SHOWN ARE 24 CLOCK CYCLES.
D
OUT
GOES LOW ON THE DCLOCK FALLING EDGE FOLLOWING THE LSB READING.
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