VIS
Description
4 (word x bit x bank), respectively.
VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
The VG36644041D, VG36648041D and VG36641641D are high-speed 67,108,864-bit synchronous
dynamic random-access memories, organized as 4,194,304 x 4 x 4, 2,097,152 x 8 x 4 and 1,048,576 x 16 x
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All input
and outputs are synchronized with the positive edge of the clock.The synchronous DRAMs are compatible
with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOPII.
Features
• Single 3.3V (
±
0.3V ) power supply
• High speed clock cycle time
-6 : 166MHz<3-3-3>, available only on 4MX16 option
-7 : 143MHz<3-3-3>, 133MHz<2-3-2>
-7L: 133MHz<3-3-3>
-8H: 100MHz<2-2-2>
• Fully synchronous operation referenced to clock rising edge
• Possible to assert random column access in every cycle
• Quad internal banks controlled by A12 & A13 (Bank Select)
• Byte control by LDQM and UDQM for VG36641641D
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable /CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• X4, X8, X16 organization
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64ms
• Burst termination by Burst stop and Precharge command
Document :1G5-0177
Rev.2
Page 1
VIS
P
in Configurations
VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
VG36644041 ( x4 )
VG36648041 ( x8 )
VG36641641 ( x16 )
V
DD
NC
V
DDQ
NC
DQ0
V
SSQ
NC
NC
V
DDQ
NC
DQ1
V
SSQ
NC
V
DD
NC
/WE
/CAS
/RAS
/CS
A13/BA0
A12/BA1
A
10
A
0
A
1
A
2
A
3
V
DD
V
DD
DQ0
V
DDQ
NC
DQ1
V
SSQ
NC
DQ2
V
DDQ
NC
DQ3
V
SSQ
NC
V
DD
NC
WE
/CAS
/RAS
/CS
A13/BA0
A12/BA1
A
10
A
0
A
1
A
2
A
3
V
DD
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
V
DD
LDQM
WE
/CAS
/RAS
/CS
A13/BA0
A12/BA1
A
10
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
NC
UDQM
CLK
CKE
NC
V
SS
DQ7
V
SSQ
NC
DQ6
V
DDQ
NC
DQ5
V
SSQ
NC
DQ4
V
DDQ
NC
V
SS
NC
DQM
CLK
CKE
NC
V
SS
NC
V
SSQ
NC
DQ3
V
DDQ
NC
NC
V
SSQ
NC
DQ2
V
DDQ
NC
V
SS
NC
DQM
CLK
CKE
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
Pin Descriptions
Pin Name
CLK
CKE
/CS
/RAS
/CAS
/WE
DQ0 ~ DQ15
Function
Master Clock
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data I/O
Pin Name
DQM
A0-11
BA0,1
V
DD
V
DDQ
V
SS
V
SSQ
Function
DQ Mask Enable
Address Input
Bank Address
Power Supply
Power Supply for DQ
Ground
Ground for DQ
Document :1G5-0177
Rev.2
Page 2
VIS
Block Diagram
CLK
CKE
Clock
Generator
VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
Address
Mode
Register
Row Decoder
Row
Address
Buffer
&
Refresh
Counter
Bank D
Bank C
Bank B
Bank A
Command Decoder
Sense Amplifier
Control Logic
Column
Address
Buffer
&
Burst
Counter
Column Decoder &
Latch Circuit
Input & Output
Buffer
Latch Circuit
CS
RAS
CAS
WE
DQM
Data Control Circuit
DQ
Document :1G5-0177
Rev.2
Page 3
VIS
Pin Function
Symbol
CLK
CKE
Input
Input
Input
VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
Function
Maste Clock: Other inputs signals are referenecd to the CLK rising edge
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals,
device input buffers and output drivers. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-
DOWN (row ACTIVE in any bank).
Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the com-
mand decoder. All commands are masked when CS# is registered HIGH. CS# provides
for external bank selection on systems with multiple banks. CS# is considered part of
the command code.
Command Inputs: RAS#, CAS# and WE# (along with CS#) define the command being
entered.
Address Inputs: Provide the row address for ACTIVE commands, and the column
address and AUTO PRECHARGE bit for READ/WRITE commands, to select one loca-
tion out of the memory array in the respective bank.
The row address is specified by A0-A11.
The column address is specified by A0-A9 (X4) / A0-A8 (X8) / A0-A7 (X16)
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
Address Inputs: Provide the row address for ACTIVE commands (row address A0-
A10), and the column address and AUTO PRECHARGE bit for READ/WRITE com-
mands (column address A0-A7 with A10 defining AUTO PRECHARGE), to select one
location out of the memory array in the respective bank.
Data Input / Output: Data bus
/CS
Input
/RAS, /CAS,
/WE
A0 - A13
Input
Input
BA0,BA1
DQM, UDQM ,
LDQM
Input
Input
DQ0 - DQ15
V
DD,
V
SS
V
DDQ,
V
SSQ
I/O
Supply Power Supply for the memory array and peripheral circuitry
Supply Power Supply are supplied to the output buffers only
Document :1G5-0177
Rev.2
Page 4
VIS
Absolute Maximum Rating
s
Parameter
Supply Voltage
Supply Voltage for Output
Input Voltage
Output Voltage
Short circuit output current
Power dissipation
Operating temperature
Storage temperature
Symbol
V
DD
V
DDQ
V
I
V
O
I
O
P
D
T
OPT
T
STG
VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
Conditions
with respect to V
SS
with respect to V
SSQ
with respect to V
SS
with respect to V
SSQ
T
a
= 25 °C
Value
-0.5 to 4.6
-0.5 to 4.6
-0.5 to V
DD
+0.5
-0.5 to V
DDQ
+0.5
50
1
0 to 70
-65 to 150
Unit
V
V
V
V
mA
W
°C
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the limits described in the operational section of this
specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions (T
a
= 0 ~ 70 °C, unless otherwise noted)
Parameter
Supply Voltage
Supply Voltage for DQ
Ground
Ground for DQ
High Level Input Voltage (all inputs)
Low Level Input Voltage (all inputs)
Symbol
V
DD
V
DDQ
V
SS
V
SSQ
V
IH
V
IL
Limits
Min.
3.0
0
3.0
0
2.0
-0.3
Typ.
3.3
0
3.3
0
Max.
3.6
0
3.6
0
V
DD
+ 0.3
0.8
Unit
V
V
V
V
V
V
Pin Capacitance (Ta = 0 ~ 70°C, V
DD
= V
DDQ
= 3.3
±
0.3V , V
SS
= V
SSQ
= 0V, unless otherwise noted)
Parameter
Input Capacitance, address & control pin
Input Capacitance, CLK pin
Data input / output capacitance
Symbol
C
IN
C
CLK
C
I/O
Min
2.5
2.5
4.0
Max
3.8
3.5
6.5
Unit
pF
pF
pF
Document :1G5-0177
Rev.2
Page 5
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