Data Sheet
January 2002
ORCA
®
Field-Programmable Ga
Features
■
■
■
■
■
■
■
■
■
■
■
High-performance, cost-effective, low-power
0.35 µm CMOS technology (OR2CxxA), 0.3 µm CMOS
technology (OR2TxxA), and 0.25 µm CMOS technology
(OR2TxxB), (four-input look-up table (LUT) delay less
than 1.0 ns with -8 speed grade)
High density (up to 43,200 usable, logic-only gates; or
99,400 gates including RAM)
Up to 480 user I/Os (OR2TxxA and OR2TxxB I/Os are
5 V tolerant to allow interconnection to both 3.3 V and
5 V devices, selectable on a per-pin basis)
Four 16-bit look-up tables and four latches/flip-flops per
PFU, nibble-oriented for implementing 4-, 8-, 16-, and/or
32-bit (or wider) bus structures
Eight 3-state buffers per PFU for on-chip bus structures
Fast, on-chip user SRAM has features to simplify RAM
design and increase RAM speed:
— Asynchronous single port: 64 bits/PFU
— Synchronous single port: 64 bits/PFU
— Synchronous dual port: 32 bits/PFU
Improved ability to combine PFUs to create larger RAM
structures using write-port enable and 3-state buffers
Fast, dense multipliers can be created with the multiplier
mode (4 x 1 multiplier/PFU):
— 8 x 8 multiplier requires only 16 PFUs
— 30% increase in speed
Flip-flop/latch options to allow programmable priority of
synchronous set/reset vs. clock enable
Enhanced cascadable nibble-wide data path
capabilities for adders, subtractors, counters, multipliers,
and comparators including internal fast-carry operation
■
■
■
■
■
■
■
■
■
Innovative, abundant, and hierarchical n
oriented routing resources that allow au
internal gates for all device densities wit
performance
Upward bit stream compatible with the
O
ATT2Txx series of devices
Pinout-compatible with new
ORCA
Serie
TTL or CMOS input levels programmabl
OR2CxxA (5 V) devices
Individually programmable drive capabil
12 mA sink/6 mA source or 6 mA sink/3
Built-in boundary scan (
IEEE
*1149.1 JT
3-state all I/O pins, (TS_ALL) testability
Multiple configuration options, including
count serial ROMs, and peripheral or JT
system programming (ISP)
Full PCI bus compliance for all devices
Supported by industry-standard CAE to
entry, synthesis, and simulation with
OR
Development System support (for back-
tion)
New, added features (OR2TxxB) have:
— More I/O per package than the OR2T
— No dedicated 5 V supply (V
DD
5)
— Faster configuration speed (40 MHz)
— Pin selectable I/O clamping diodes pr
PCI compliance and 5V tolerance
— Full PCI bus compliance in both 5V a
tems
*
IEEE
is a registered trademark of The Institut
Electronics Engineers, Inc.
Table 1
. ORCA
Series 2 FPGAs
Device
OR2C04A/OR2T04A
OR2C06A/OR2T06A
OR2C08A/OR2T08A
OR2C10A/OR2T10A
OR2C12A/OR2T12A
OR2C15A/OR2T15A/OR2T15B
OR2C26A/OR2T26A
OR2C40A/OR2T40A/OR2T40B
Usable
Gates*
4,800—11,000
6,900—15,900
9,400—21,600
12,300—28,300
15,600—35,800
19,200—44,200
27,600—63,600
43,200—99,400
# LUTs
400
576
784
1024
1296
1600
2304
3600
Registers
400
576
724
1024
1296
1600
2304
3600
Max User
RAM Bits
6,400
9,216
12,544
16,384
20,736
25,600
36,864
57,600
User
I/Os
160
192
224
256
288
320
384
480
* The first number in the usable gates column assumes 48 gates per PFU (12 gates per four-input LUT/FF pair) for logic
second number assumes 30% of a design is RAM. PFUs used as RAM are counted at four gates per bit, with each P
implementing a 16 x 4 RAM (or 256 gates) per PFU.
ORCA
Series 2 FPGAs
Data
January
Table of Contents
Contents
Page
Contents
Features ...................................................................... 1
Description................................................................... 3
ORCA
Foundry Development System Overview......... 5
Architecture ................................................................. 5
Programmable Logic Cells .......................................... 5
Programmable Function Unit ................................... 5
Look-Up Table Operating Modes ............................ 7
Latches/Flip-Flops ................................................. 15
PLC Routing Resources ........................................ 17
PLC Architectural Description................................ 22
Programmable Input/Output Cells ............................. 25
Inputs..................................................................... 25
Outputs .................................................................. 26
5 V Tolerant I/O (OR2TxxB) .................................. 27
PCI Compliant I/O.................................................. 27
PIC Routing Resources ......................................... 28
PIC Architectural Description................................. 29
PLC-PIC Routing Resources................................. 30
Interquad Routing ...................................................... 32
Subquad Routing (OR2C40A/OR2T40A Only)...... 34
PIC Interquad (MID) Routing ................................. 36
Programmable Corner Cells ...................................... 37
Programmable Routing.......................................... 37
Special-Purpose Functions.................................... 37
Clock Distribution Network ........................................ 37
Primary Clock ........................................................ 37
Secondary Clock ................................................... 38
Selecting Clock Input Pins..................................... 39
FPGA States of Operation......................................... 40
Initialization............................................................ 40
Configuration ......................................................... 41
Start-Up ................................................................. 42
Reconfiguration ..................................................... 42
Partial Reconfiguration .......................................... 43
Other Configuration Options.................................. 43
Configuration Data Format ........................................ 43
Using
ORCA
Foundry to Generate
Configuration RAM Data..................................... 44
Configuration Data Frame ..................................... 44
Bit Stream Error Checking......................................... 47
FPGA Configuration Modes....................................... 47
Master Parallel Mode............................................. 47
Master Serial Mode ............................................... 48
Asynchronous Peripheral Mode ............................ 49
Synchronous Peripheral Mode .............................. 49
Slave Serial Mode ................................................. 50
Slave Parallel Mode............................................... 50
Daisy Chain ........................................................... 51
Special Function Blocks ............................................ 52
Single Function Blocks .......................................... 52
Boundary Scan ...................................................... 54
2
Boundary-Scan Instructions...........................
ORCA
Boundary-Scan Circuitry ....................
ORCA
Timing Characteristics............................
Estimating Power Dissipation ............................
OR2CxxA.......................................................
OR2TxxA .......................................................
OR2T15B and OR2T40B...............................
Pin Information ..................................................
Pin Descriptions.............................................
Package Compatibility ...................................
Compatibility with Series 3 FPGAs ................
Package Thermal Characteristics......................
QJA ................................................................
yJC.................................................................
QJC................................................................
QJB................................................................
Package Coplanarity .........................................
Package Parasitics ............................................
Absolute Maximum Ratings ...............................
Recommended Operating Conditions ...............
Electrical Characteristics ...................................
Timing Characteristics .......................................
Series 2..........................................................
Measurement Conditions...................................
Output Buffer Characteristics ............................
OR2CxxA.......................................................
OR2TxxA .......................................................
OR2TxxB .......................................................
Package Outline Drawings ................................
Terms and Definitions....................................
84-Pin PLCC..................................................
100-Pin TQFP................................................
144-Pin TQFP................................................
160-Pin QFP ..................................................
208-Pin SQFP................................................
208-Pin SQFP2..............................................
240-Pin SQFP................................................
240-Pin SQFP2..............................................
256-Pin PBGA ...............................................
304-Pin SQFP................................................
304-Pin SQFP2..............................................
352-Pin PBGA ...............................................
432-Pin EBGA ...............................................
Ordering Information..........................................
Index ..................................................................
Lattice Semico
Data Sheet
January 2002
ORCA
Ser
Description
The
ORCA
Series 2 series of SRAM-based FPGAs are
an enhanced version of the ATT2C/2T architecture.
The latest
ORCA
series includes patented architectural
enhancements that make functions faster and easier to
design while conserving the use of PLCs and routing
resources.
The Series 2 devices can be used as drop-in replace-
ments for the ATT2Cxx/ATT2Txx series, respectively,
and they are also bit stream compatible with each
other. The usable gate counts associated with each
series are provided in Table 1. Both series are offered
in a variety of packages, speed grades, and tempera-
ture ranges.
The
ORCA
series FPGA consists of two basic ele-
ments: programmable logic cells (PLCs) and program-
Table 2
. ORCA
Series 2 System Performance
Function
16-bit loadable up/down
counter
16-bit accumulator
8 x 8 parallel multiplier:
— Multiplier mode,
unpipelined
1
— ROM mode, unpipelined
2
— Multiplier mode, pipelined
3
32 x 16 RAM:
— Single port (read and write/
cycle)
4
— Single port
5
— Dual port
6
36-bit parity check (internal)
32-bit address decode
(internal)
1.
2.
3.
4.
5.
6.
7.
8.
mable input/output cells (PICs). An arra
surrounded by PICs as shown in Figure
contains a programmable function unit (
PLCs and PICs also contain routing res
configuration RAM. All logic is done in t
PFU contains four 16-bit look-up tables (
latches/flip-flops (FFs).
The PLC architecture provides a balanc
and routing that allows a higher utilized
alternative architectures. The routing re
logic signals between PFUs and I/O pad
in the PLC is symmetrical about the hor
tical axes. This improves routability by a
signals to be routed into the PLC from a
Some examples of the resources requir
formance that can be achieved using the
represented in Table 2.
#
PFUs
Speed Grade
-2A
51.0
51.0
14.2
41.5
50.5
-3A
66.7
66.7
19.3
55.6
69.0
-4A
87.0
87.0
25.1
71.9
82.0
-5A
104.2
104.2
31.0
87.7
103.1
-6A
129.9
129.9
36.0
107.5
125.0
-7A
144.9
144.9
40.3
122.0
142.9
-7B
4
4
22
9
44
131
131
37
103
123
9
9
16
4
3.25
21.8
38.2
38.2
13.9
12.3
28.6
52.6
52.6
11.0
9.5
36.2
69.0
83.3
9.1
7.5
53.8
92.6
92.6
7.4
6.1
53.8
92.6
92.6
5.6
4.6
62.5
96.2
96.2
5.2
4.3
57
97
97
6.
4.
Implemented using 4 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
Implemented using two 16 x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.
Implemented using 4 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (28 of 44 PFUs contain only p
Implemented using 16 x 4 synchronous single-port RAM mode allowing both read and write per clock cycle, including wr
multiplexer.
Implemented using 16 x 4 synchronous single-port RAM mode allowing either read or write per clock cycle, including writ
tiplexer.
Implemented using 16 x 2 synchronous dual-port RAM mode.
OR2TxxB available only in -7 and -8 speeds only.
Speed grades of -5, -6, and -7 are for OR2TxxA devices only.
Lattice Semiconductor
ORCA
Series 2 FPGAs
Data
January
Description
(continued)
The FPGA’s functionality is determined by internal configuration RAM. The FPGA’s internal initialization/con
tion circuitry loads the configuration data at powerup or under system control. The RAM is loaded by using
several configuration modes. The configuration data resides externally in an EEPROM, EPROM, or ROM o
circuit board, or any other storage media. Serial ROMs provide a simple, low pin count method for configuri
FPGAs, while the peripheral and JTAG configuration modes allow for easy, in-system programming (ISP).
PT1
PL1
R1C1
PT2
R1C2
PT3
R1C3
PT4
R1C4
PT5
R1C5
PT6
R1C6
PT7
R1C7
PT8
R1C8
PT9
R1C9
TMID
PT10
PT11
PT12
PT13
PT14
PT15
PT16
PT17
PT18
R1C18
R1C10 R1C11 R1C12 R1C13 R1C14 R1C15 R1C16 R1C17
PL2
R2C1
R2C2
R2C3
R2C4
R2C5
R2C6
R2C7
R2C8
R2C9
vIQ
R2C10 R2C11 R2C12 R2C13 R2C14 R2C15 R2C16 R2C17
R2C18
PL3
R3C1
R3C2
R3C3
R3C4
R3C5
R3C6
R3C7
R3C8
R3C9
R3C10 R3C11 R3C12 R3C13 R3C14 R3C15 R13C16 R3C17
R3C18
PL4
R4C1
R4C2
R4C3
R4C4
R4C5
R4C6
R4C7
R4C8
R4C9
R4C10 R4C11 R4C12 R4C13 R4C14 R4C15 R4C16 R4C17
R4C18
PL5
R5C1
R5C2
R5C3
R5C4
R5C5
R5C6
R5C7
R5C8
R5C9
R5C10 R5C11 R5C12 R5C13 R5C14 R5C15 R5C16 R5C17
R5C18
PL6
R6C1
R6C2
R6C3
R6C4
R6C5
R6C6
R6C7
R6C8
R6C9
R6C10 R6C11 R6C12 R6C13 R6C14 R6C15 R6C16 R6C17
R6C18
PL7
R7C1
R7C2
R7C3
R7C4
R7C5
R7C6
R7C7
R7C8
R7C9
R7C10 R7C11 R7C12 R7C13 R7C14 R7C15 R7C16 R7C17
R7C18
PL8
R8C1
R8C2
R8C3
R8C4
R8C5
R8C6
R8C7
R8C8
R8C9
R8C10 R8C11 R8C12 R8C13 R8C14 R8C15 R8C16 R8C17
R8C18
PL9
R9C1
R9C2
R9C3
R9C4
R9C5
R9C6
R9C7
R9C8
R9C9
R9C10 R9C11 R9C12 R9C13 R9C14 R9C15 R9C16 R9C17
R9C18
LMID
hIQ
PL10
R10C1 R10C2 R10C3
R10C4 R10C5 R10C6
R10C7 R10C8 R10C9
R10C10 R10C11 R10C12 R10C13 R10C14 R10C15 R10C16 R10C17 R10C18
PL11
R11C1 R11C2 R11C3
R11C4 R11C5 R11C6 R11C7 R11C8 R11C9
R11C10 R11C11 R11C12 R11C13 R11C14 R11C15 R11C16 R11C17 R11C18
PL12
R12C1 R12C2 R12C3
R12C4 R12C5 R12C6 R12C7 R12C8 R12C9
R12C10 R12C11 R12C12 R12C13 R12C14 R12C15 R12C16 R12C17 R12C18
PL13
R13C1 R13C2 R13C3
R13C4 R13C5 R13C6 R13C7 R13C8 R13C9
R13C10 R13C11 R13C12 R13C13 R13C14 R13C15 R13C16 R13C17 R13C18
PL14
R14C1 R14C2 R14C3
R14C4 R14C5 R14C6 R14C7 R14C8 R14C9
R14C10 R14C11 R14C12 R14C13 R14C14 R14C15 R14C16 R14C17 R14C18
PL15
R15C1 R15C2 R15C3
R15C4 R15C5 R15C6 R15C7 R15C8 R15C9
R15C10 R15C11 R15C12 R15C13 R15C14 R15C15 R15C16 R15C17 R15C18
PL16
R16C1 R16C2 R16C3
R16C4 R16C5 R16C6 R16C7 R16C8 R16C9
R16C10 R16C11 R16C12 R16C13 R16C14 R16C15 R16C16 R16C17 R16C18
PL17
R17C1 R17C2 R17C3
R17C4 R17C5 R17C6 R17C7 R17C8 R17C9
R17C10 R17C11 R17C12 R17C13 R17C14 R17C15 R17C16 R17C17 R17C18
PL18
R18C1 R18C2 R18C3
PB1
PB2
PB3
R18C4 R18C5 R18C6 R18C7 R18C8 R18C9
PB4
PB5
PB6
PB7
PB8
PB9
PB10
R18C10 R18C11 R18C12 R18C13 R18C14 R18C15 R18C16 R18C17 R18C18
BMID
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
Figure 1. Series 2 Array
4
Lattice Semico
Data Sheet
January 2002
ORCA
Ser
ORCA
Foundry
Development System
Overview
The
ORCA
Foundry Development System interfaces to
front-end design entry tools and provides the tools to
produce a configured FPGA. In the design flow, the
user defines the functionality of the FPGA at two
points: at design entry and at the bit stream generation
stage.
Following design entry, the development system’s map,
place, and route tools translate the netlist into a routed
FPGA. Its bit stream generator is then used to generate
the configuration data which is loaded into the FPGA’s
internal configuration RAM. When using the bit stream
generator, the user selects options that affect the func-
tionality of the FPGA. Combined with the front-end
tools,
ORCA
Foundry produces configuration data that
implements the various logic and routing options dis-
cussed in this data sheet.
binatorial mode, the LUTs can realize a
or six-input logic functions. In ripple mod
speed carry logic is used for arithmetic
new multiplier function, or the enhanced
functions. In memory mode, the LUTs ca
16 x 4 read/write or read-only memory (
mode or the new synchronous mode) o
dual-port memory.
Programmable Logic Cells
The programmable logic cell (PLC) con
grammable function unit (PFU) and rou
All PLCs in the array are identical. The P
tains four LUTs and four latches/FFs for
mentation, is discussed in the next sect
Programmable Function Unit
Architecture
The
ORCA
Series FPGA is comprised of two basic
elements: PLCs and PICs. Figure 1 shows an array of
programmable logic cells (PLCs) surrounded by pro-
grammable input/output cells (PICs). The Series 2 has
PLCs arranged in an array of 20 rows and 20 columns.
PICs are located on all four sides of the FPGA between
the PLCs and the IC edge.
The location of a PLC is indicated by its row and col-
umn so that a PLC in the second row and third column
is R2C3. PICs are indicated similarly, with PT (top) and
PB (bottom) designating rows and PL (left) and PR
(right) designating columns, followed by a number. The
routing resources and configuration RAM are not
shown, but the interquad routing blocks (hIQ, vIQ)
present in the Series 2 series are shown.
Each PIC contains the necessary I/O buffers to inter-
face to bond pads. The PICs also contain the routing
resources needed to connect signals from the bond
pads to/from PLCs. The PICs do not contain any user-
accessible logic elements, such as flip-flops.
Combinatorial logic is done in look-up tables (LUTs)
located in the PFU. The PFU can be used in different
modes to meet different logic requirements. The LUT’s
configurable medium-/large-grain architecture can be
used to implement from one to four combinatorial logic
functions. The flexibility of the LUT to handle wide input
functions, as well as multiple smaller input functions,
maximizes the gate count/PFU.
The LUTs can be programmed to operate in one of
three modes: combinatorial, ripple, or memory. In com-
Lattice Semiconductor
The PFUs are used for logic. Each PFU
nal inputs and six outputs and can oper
modes. The functionality of the inputs a
depends on the operating mode.
The PFU uses three input data buses (A
WD[3:0]), four control inputs (C0, CK, C
carry input (CIN); the last is used for fas
functions. There is a 5-bit output bus (O
carry-out (COUT).
PROGRAMMABLE LOGIC CELL (
WD3
WD2
WD1
WD0
A4
A3
A2
A1
A0
B4
B3
B2
B1
B0
CIN
C0 CK CE LSR
C
PROGRAMMABLE
FUNCTION UNIT
(PFU)
(ROUTING RESOURCES, CONFIGURA
Figure 2. PFU Ports
Analogue and Mixed Signal
京公网安备 11010802033920号
EEWORLD
