Changes to Ordering Guide .......................................................... 17
11/03—Rev. 0 to Rev. A
Changes to Electrical Characteristics ............................................ 3
11/03—Revision 0: Initial Version
Rev. C | Page 2 of 20
AD5162
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS: 2.5 kΩ VERSION
V
DD
= 5 V ± 10%, or 3 V ± 10%; V
A
= V
DD
; V
B
= 0 V; −40°C < T
A
< +125°C; unless otherwise noted.
Table 1.
Parameter
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity
2
Resistor Integral Nonlinearity
2
Nominal Resistor Tolerance
3
Resistance Temperature Coefficient
Wiper Resistance
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
4
Differential Nonlinearity
5
Integral Nonlinearity
5
Voltage Divider Temperature
Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range
6
Capacitance A, B
7
Capacitance W
7
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance
7
POWER SUPPLIES
Power Supply Range
Supply Current
Power Dissipation
8
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS
9
Bandwidth, −3 dB
Total Harmonic Distortion
V
W
Settling Time
Resistor Noise Voltage Density
1
2
Symbol
R-DNL
R-INL
∆R
AB
(∆R
AB
/R
AB
)/∆T
R
WB
Conditions
R
WB
, V
A
= no connect
R
WB
, V
A
= no connect
T
A
= 25°C
V
AB
= V
DD
, wiper = no connect
Code = 0x00, V
DD
= 5 V
Min
−2
−14
−20
Typ
1
±0.1
±2
35
160
Max
+2
+14
+55
200
Unit
LSB
LSB
%
ppm/°C
Ω
DNL
INL
(∆V
W
/V
W
)/∆T
V
WFSE
V
WZSE
V
A
, V
B
, V
W
C
A
, C
B
C
W
I
CM
V
IH
V
IL
V
IH
V
IL
I
IL
C
IL
V
DD RANGE
I
DD
P
DISS
PSS
BW
THD
W
t
S
e
N_WB
−1.5
−2
Code = 0x80
Code = 0xFF
Code = 0x00
−14
0
GND
f = 1 MHz, measured to GND,
code = 0x80
f = 1 MHz, measured to GND,
code = 0x80
V
A
= V
B
= V
DD
/2
V
DD
= 5 V
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 3 V
V
IN
= 0 V or 5 V
2.4
±0.1
±0.6
15
−5.5
4.5
+1.5
+2
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
nA
V
V
V
V
µA
pF
V
µA
µW
%/%
MHz
%
µs
nV/√Hz
0
12
V
DD
45
60
1
0.8
2.1
0.6
±1
5
2.7
5.5
6
30
±0.08
V
IH
= 5 V or V
IL
= 0 V
V
IH
= 5 V or V
IL
= 0 V, V
DD
= 5 V
V
DD
= 5 V ± 10%, code = midscale
Code = 0x80
V
A
= 1 V rms, V
B
= 0 V, f = 1 kHz
V
A
= 5 V, V
B
= 0 V, ±1 LSB error band
R
WB
= 1.25 kΩ, R
S
= 0
3.5
±0.02
4.8
0.1
1
3.2
Typical specifications represent average readings at 25°C and V
DD
= 5 V.
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
A
= V
DD
, V
B
= 0 V, wiper (V
W
) = no connect.
4
Specifications apply to all VRs.
5
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
A
= V
DD
and V
B
= 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
6
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
7
Guaranteed by design, but not subject to production test.
8
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
9
All dynamic characteristics use V
DD
= 5 V.
Rev. C | Page 3 of 20
AD5162
ELECTRICAL CHARACTERISTICS: 10 kΩ, 50 kΩ, AND 100 kΩ VERSIONS
V
DD
= 5 V ± 10%, or 3 V ± 10%; V
A
= V
DD
; V
B
= 0 V; −40°C < T
A
< 125°C; unless otherwise noted.
Table 2.
Parameter
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity
2
Resistor Integral Nonlinearity
2
Nominal Resistor Tolerance
3
Resistance Temperature Coefficient
Wiper Resistance
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
4
Differential Nonlinearity
5
Integral Nonlinearity
5
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range
6
Capacitance A, B
7
Capacitance W
7
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance
POWER SUPPLIES
Power Supply Range
Supply Current
Power Dissipation
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS
Bandwidth, −3 dB
Total Harmonic Distortion
V
W
Settling Time
Resistor Noise Voltage Density
1
2
Symbol
R-DNL
R-INL
∆R
AB
(∆R
AB
/R
AB
)/∆T
R
WB
Conditions
R
WB
, V
A
= no connect
R
WB
, V
A
= no connect
T
A
= 25°C
V
AB
= V
DD
, wiper = no connect
Code = 0x00, V
DD
= 5 V
Min
−1
−2.5
−20
Typ
1
±0.1
±0.25
35
160
Max
+1
+2.5
+20
200
Unit
LSB
LSB
%
ppm/°C
Ω
DNL
INL
(∆V
W
/V
W
)/∆T
V
WFSE
V
WZSE
V
A
, V
B
, V
W
C
A
, C
B
C
W
I
CM
V
IH
V
IL
V
IH
V
IL
I
IL
C
IL
V
DD RANGE
I
DD
P
DISS
PSS
BW
THD
W
t
S
e
N_WB
−1
−1
Code = 0x80
Code = 0xFF
Code = 0x00
−2.5
0
GND
f = 1 MHz, measured to GND,
code = 0x80
f = 1 MHz, measured to GND,
code = 0x80
V
A
= V
B
= V
DD
/2
V
DD
= 5 V
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 3 V
V
IN
= 0 V or 5 V
2.4
±0.1
±0.3
15
−1
1
+1
+1
0
2.5
V
DD
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
nA
V
V
V
V
µA
pF
V
µA
µW
%/%
kHz
%
µs
nV/√Hz
45
60
1
0.8
2.1
0.6
±1
5
2.7
5.5
6
30
±0.08
V
IH
= 5 V or V
IL
= 0 V
V
IH
= 5 V or V
IL
= 0 V, V
DD
= 5 V
V
DD
= 5 V ± 10%, code = midscale
R
AB
= 10 kΩ/50 kΩ/100 kΩ,
code = 0x80
V
A
= 1 V rms, V
B
= 0 V,
f = 1 kHz, R
AB
= 10 kΩ
V
A
= 5 V, V
B
= 0 V,
±1 LSB error band
R
WB
= 5 kΩ, R
S
= 0
3.5
±0.02
600/100/40
0.1
2
9
Typical specifications represent average readings at 25°C and V
DD
= 5 V.
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
A
= V
DD
, V
B
= 0 V, wiper (V
W
) = no connect.
4
Specifications apply to all VRs.
5
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
A
= V
DD
and V
B
= 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
6
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
7
Guaranteed by design, but not subject to production test.
Rev. C | Page 4 of 20
AD5162
TIMING CHARACTERISTICS: ALL VERSIONS
V
DD
= 5 V ± 10%, or 3 V ± 10%; V
A
= V
DD
; V
B
= 0 V; −40°C < T
A
< +125°C; unless otherwise noted.
Table 3.
Parameter
SPI INTERFACE TIMING CHARACTERISTICS
1
Clock Frequency
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CS Setup Time
CS High Pulse Width
CLK Fall to CS Fall Hold Time
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
1
Symbol
f
CLK
t
CH
, t
CL
t
DS
t
DH
t
CSS
t
CSW
t
CSH0
t
CSH1
t
CS1
Conditions
Min
Typ
Max
25
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock level high or low
20
5
5
15
40
0
0
10
See the timing diagrams for the locations of measured values (that is, see Figure 42 and Figure 43).
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