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CY7C1081DV33-12BAXIT

Categorystorage   
File Size271KB,12 Pages
ManufacturerCypress Semiconductor
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CY7C1081DV33-12BAXIT Parametric

Parameter NameAttribute value
Product CategorySRAM
ManufacturerCypress Semiconductor
RoHSDetails
Memory Size64 Mbit
Organization4 M x 16
Access Time12 ns
Interface TypeParallel
Supply Voltage - Max3.6 V
Supply Voltage - Min3 V
Supply Current - Max300 mA
Minimum Operating Temperature- 40 C
Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT
Package / CaseFBGA-48
PackagingReel
Memory TypeSDR
Factory Pack Quantity2000
TypeAsynchronous
CY7C1081DV33
64-Mbit (4 M × 16) Static RAM
Features
Functional Description
The CY7C1081DV33 is a high-performance CMOS static RAM
organized as 4,194,304 words by 16 bits.
To write to the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
) is
written into the location specified on the address pins (A
0
through
A
21
). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O
8
through I/O
15
) is written into the location specified on the
address pins (A
0
through A
21
).
To read from the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O
8
to I/O
15
. See the
Truth Table on page
9
for a complete description of read and write modes.
The input and output pins (I/O
0
through I/O
15
) are placed in a
high impedance state when the device is deselected (CE
1
HIGH
or CE
2
LOW), the outputs are disabled (OE HIGH), both byte
high enable and byte low enable are disabled (BHE, BLE HIGH),
or during a write operation (CE
1
LOW, CE
2
HIGH, and WE
LOW).
High speed
t
AA
= 12 ns
Low active power
I
CC
= 300 mA at 12 ns
Low complementary metal oxide semiconductor (CMOS)
standby power
I
SB2
= 100 mA
Operating voltages of 3.3 ± 0.3 V
2.0-V data retention
Automatic power-down when deselected
Transistor-transistor logic (TTL)-compatible inputs and outputs
Easy memory expansion with CE
1
and CE
2
features
Available in Pb-free 48-ball fine ball grid array (FBGA) package
Logic Block Diagram
DATA
IN
DRIVERS
ROW DECODER
4M × 16
SENSE AMPS
A
(10:0)
RAM ARRAY
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
BHE
WE
OE
BLE
A
(21:11)
CE
2
CE
1
Cypress Semiconductor Corporation
Document #: 001-53992 Rev. *D
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised August 22, 2012
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