STNRG288ATR datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Analog mixed-signal IC> The signal circuit> STNRG288ATR

STNRG288ATR: CategoryAnalog mixed-signal IC The signal circuit; File Size3MB，131 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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STNRG288ATR Parametric

Parameter Name	Attribute value
Brand Name	STMicroelectronics
Maker	STMicroelectronics
package instruction	TSSOP, TSSOP28,.25
Reach Compliance Code	compliant
ECCN code	3A991.A.2
Factory Lead Time	12 weeks
Analog Integrated Circuits - Other Types	ANALOG CIRCUIT
JESD-30 code	R-PDSO-G28
Number of terminals	28
Maximum operating temperature	105 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP28,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3/5 V
Certification status	Not Qualified
Maximum supply current (Isup)	12.74 mA
surface mount	YES
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED

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STNRGxxxA

Digital controller for power conversion applications

with up to 6 programmable PWM generators, 96 MHz PLL

Datasheet

production data

– Data memory: 1 Kbyte true data E

PROM;

data retention:15 years at 85 °C after 100

kcycles at 85 °C

– RAM: 6 Kbytes



Clock management

– Internal 96 MHz PLL

– Low power oscillator circuit for external

crystal resonator or direct clock input

– Internal, user-trimmable 16 MHz RC and

low power 153.6 kHz RC oscillators

– Clock security system with clock monitor



Basic peripherals

– System, auxiliary and basic timers

– IWDG/WWDG watchdog, AWU, ITC



Reset and supply management

– Multiple low power modes (wait, slow, auto-

wakeup, Halt) with user definable clock

gating

– Low consumption power-on and power-

down reset



I/O

– Multifunction bidirectional GPIO with highly

robust design, immune against current

injection

– Fast digital input DIGIN, with configurable

pull-up



Communication interfaces

– UART asynchronous with SW flow control

and bootloader support

– I

C master/slave fast-slow speed rate



Operating temperature: -40 °C up to 105 °C.

Table 1. Device summary

Part number

STNRG388A

STNRG328A

STNRG288A

Package

TSSOP38

VFQFPN32

TSSOP28

Features



Up to 6 programmable PWM generators

(SMED - “State Machine Event Driven”)

– 10 ns event detection and reaction

– Max.1.3 ns PWM resolution

– Single, coupled and two coupled

operational modes

– Up to 3 internal/external events per SMED



4 analog comparators

– 4 internal 4-bit references

– Up to 4 external references

– Less than 50 ns propagation time

– Continuous comparison cycle

– Configurable hysteresis voltage levels



ADCs (up to 8 channels)

– 10-bit precision, with operational amplifier

to extend resolution to 12-bit equivalent

– Sequencer functionality

– Input impedance: 1 M

– Configurable gain value: x1 and x4



Integrated microcontroller

– Advanced STM8

core with Harvard

architecture and 3-stage pipeline

– Max. f

CPU

: 16 MHz



Memories

– Flash and E

PROM with read while write

(RWW) and error correction code (ECC)

– Program memory: 32 Kbytes Flash; data

retention 15 years at 85 °C after 10 kcycles

at 25 °C

October 2016

This is information on a product in full production.

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www.st.com

Contents

STNRGxxxA

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

STNRG family features list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Introducing SMED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.1

SMED (state machine event driven): configurable PWM generator . . . . . 16

5.1.1

5.1.2

SMED coupling schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Connection matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Architecture and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Single wire interface module (SWIM) . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Debug module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Vectored interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Flash program and data E

PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Write protection (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Protection of user boot code (UBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Read-out protection (ROP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Internal 16 MHz RC oscillator (HSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Internal 153.6 kHz RC oscillator (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Internal 96 MHz PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

External clock input/crystal oscillator (HSE) . . . . . . . . . . . . . . . . . . . . . 25

5.2

Internal controller (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.2.1

5.2.2

5.2.3

5.2.4

5.2.5

5.3

Basic peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

5.3.7

5.4

Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.4.1

5.4.2

5.4.3

5.4.4

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Contents

5.5

5.6

Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.6.1

5.6.2

5.6.3

Universal asynchronous receiver/transmitter (UART) . . . . . . . . . . . . . . 27

Inter-integrated circuit interface (I

C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Digital addressable lighting interface (DALI) . . . . . . . . . . . . . . . . . . . . . 28

5.7

5.8

Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Analog comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.1

6.2

6.3

Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Input/output specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

I/O multifunction signal configuration . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.1

7.2

Multifunction configuration policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Port P0 I/O multifunction configuration signal . . . . . . . . . . . . . . . . . . . . . 37

7.2.1

7.2.2

7.2.3

7.2.4

7.2.5

Alternate function P0 configuration signals . . . . . . . . . . . . . . . . . . . . . . 37

Port P0 diagnostic signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Port P0 I/O functional multiplexing signal . . . . . . . . . . . . . . . . . . . . . . . 39

P0 interrupt capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

P0 programmable pull-up and speed feature . . . . . . . . . . . . . . . . . . . . 39

Port P1 I/O multiplexing signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

P1 interrupt capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

P1 programmable pull-up feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

P2 ADC hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

P2 interrupt capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

P2 programmable pull-up feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

P3 ADC conversion request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

P3 interrupt capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.3

Port P1 I/O multifunction configuration signal . . . . . . . . . . . . . . . . . . . . . 40

7.3.1

7.3.2

7.3.3

7.4

Port P2 I/O multifunction configuration signal . . . . . . . . . . . . . . . . . . . . . 41

7.4.1

7.4.2

7.4.3

7.5

Port P3 analog signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.5.1

7.5.2

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STNRGxxxA

7.6

Multifunction port configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . 44

MSC_IOMXP0 (Port P1 I/O MUX control register). . . . . . . . . . . . . . . . . . . . . . . . . 44

MSC_IOMXP1 (Port P1 I/O MUX control register). . . . . . . . . . . . . . . . . . . . . . . . . 45

MSC_IOMXP2 (Port P2 I/O MUX control register). . . . . . . . . . . . . . . . . . . . . . . . . 46

MSC_INPP2AUX1 (INPP aux register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8.1

8.2

Memory map overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8.2.1

8.2.2

8.2.3

8.2.4

8.2.5

8.2.6

8.2.7

8.2.8

8.2.9

8.2.10

8.2.11

8.2.12

8.2.13

8.2.14

8.2.15

8.2.16

8.2.17

8.2.18

8.2.19

8.2.20

8.2.21

8.2.22

8.2.23

General purpose I/O GPIO0 register map . . . . . . . . . . . . . . . . . . . . . . . 50

General purpose I/O GPIO1 register map . . . . . . . . . . . . . . . . . . . . . . . 50

Miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Flash and E

PROM non-volatile memories . . . . . . . . . . . . . . . . . . . . . . 54

Reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Clock controller register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

WWDG timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

IWDG timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

AWU timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Inter-integrated circuit interface (I

C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Universal asynchronous receiver/transmitter (UART) . . . . . . . . . . . . . . 57

System timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Auxiliary timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Basic timer0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Basic timer1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Digital addressable lighting interface (DALI) . . . . . . . . . . . . . . . . . . . . . 59

DALI noise rejection filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

State machine event driven (SMEDs) . . . . . . . . . . . . . . . . . . . . . . . . . . 61

CPU register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Global configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

SWIM control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

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Contents

Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.1

10.2

Option byte register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Option byte register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

10.2.1

10.2.2

10.2.3

10.2.4

10.2.5

10.2.6

10.2.7

10.2.8

10.2.9

ROP (memory read-out protection register) . . . . . . . . . . . . . . . . . . . . . 71

UBC (UBC user boot code register) . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

nUBC (UBC user boot code register protection) . . . . . . . . . . . . . . . . . . 72

GENCFG (general configuration register) . . . . . . . . . . . . . . . . . . . . . . . 72

nGENCFG (general configuration register protection) . . . . . . . . . . . . . . 73

MISCUOPT (miscellaneous configuration register) . . . . . . . . . . . . . . . . 73

nMISCUOPT (miscellaneous configuration register protection) . . . . . . 74

CLKCTL (CKC configuration register) . . . . . . . . . . . . . . . . . . . . . . . . . . 74

nCLKCTL (CKC configuration register protection) . . . . . . . . . . . . . . . . . 75

10.2.10 HSESTAB (HSE clock stabilization register) . . . . . . . . . . . . . . . . . . . . . 75

10.2.11 nHSESTAB (HSE clock stabilization register protection) . . . . . . . . . . . . 76

10.2.12 ENHFEAT (EXP features configuration register) . . . . . . . . . . . . . . . . . . 76

10.2.13 nENHFEAT (EXP features configuration register) . . . . . . . . . . . . . . . . . 77

10.2.14 WAITSTATE (Flash wait state register) . . . . . . . . . . . . . . . . . . . . . . . . . 77

10.2.15 nWAITSTATE (Flash wait state register protection) . . . . . . . . . . . . . . . . 78

10.2.16 AFR_IOMXP0 (alternative Port0 configuration register) . . . . . . . . . . . . 78

10.2.17 nAFR_IOMXP0 (alternative Port0 configuration register protection) . . . 79

10.2.18 AFR_IOMXP1 (alternative Port1 configuration register) . . . . . . . . . . . . 79

10.2.19 nAFR_IOMXP1 (alternative Port1 configuration register protection) . . . 80

10.2.20 AFR_IOMXP2 (alternative Port2 configuration register) . . . . . . . . . . . . 80

10.2.21 nAFR_IOMXP2 (alternative Port2 configuration register protection) . . . 81

10.2.22 MSC_OPT0 (miscellaneous configuration reg0) . . . . . . . . . . . . . . . . . . 81

10.2.23 nMSC_OPT0 (miscellaneous configuration reg0 protection) . . . . . . . . . 82

10.2.24 OPTBL (option byte bootloader) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

10.2.25 nOPTBL (option byte boot loader protection) . . . . . . . . . . . . . . . . . . . . 83

Device identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

11.1

11.2

Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

12.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

12.1.1

12.1.2

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

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