SC16C754
Quad UART with 64-byte FIFO
Rev. 04 — 19 June 2003
Product data
1. Description
The SC16C754 is a quad universal asynchronous receiver/transmitter (UART) with
64-byte FIFOs, automatic hardware/software flow control, and data rates up to
5 Mbits/s (3.3 V and 5 V). The SC16C754 offers enhanced features. It has a
transmission control register (TCR) that stores receiver FIFO threshold levels to
start/stop transmission during hardware and software flow control. With the FIFO
RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one
access. On-chip status registers provide the user with error indications, operational
status, and modem interface control. System interrupts may be tailored to meet user
requirements. An internal loop-back capability allows on-board diagnostics.
The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and
receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or
8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be
programmed to interrupt at different trigger levels. The UART generates its own
desired baud rate based upon a programmable divisor and its input clock. It can
transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect
break, idle, or framing errors, FIFO overflow, and parity errors. The transmitter can
detect FIFO underflow. The UART also contains a software interface for modem
control operations, and has software flow control and hardware flow control
capabilities.
The SC16C754 is available in plastic LQFP80 and PLCC68 packages.
2. Features
s
Pin compatible with SC16C654IA68 and SC16C554IA68 with additional
enhancements
s
Up to 5 Mbits/s baud rate (at 3.3 V and 5 V; at 2.5 V maximum baud rate is
3 Mbits/s)
s
64-byte transmit FIFO
s
64-byte receive FIFO with error flags
s
Programmable and selectable transmit and receive FIFO trigger levels for DMA
and interrupt generation
s
Software/hardware flow control
x
Programmable Xon/Xoff characters
x
Programmable auto-RTS and auto-CTS
s
Optional data flow resume by Xon any character
s
DMA signalling capability for both received and transmitted data
s
Supports 5 V, 3.3 V and 2.5 V operation
s
Software selectable baud rate generator
Philips Semiconductors
SC16C754
Quad UART with 64-byte FIFO
s
s
s
s
s
s
s
s
s
s
Prescaler provides additional divide-by-4 function
Fast databus access time
Programmable sleep mode
Programmable serial interface characteristics
x
5, 6, 7, or 8-bit characters
x
Even, odd, or no parity bit generation and detection
x
1, 1.5, or 2 stop bit generation
False start bit detection
Complete status reporting capabilities in both normal and sleep mode
Line break generation and detection
Internal test and loop-back capabilities
Fully prioritized interrupt system controls
Modem control functions (CTS, RTS, DSR, DTR, RI, and CD).
3. Ordering information
Table 1:
Ordering information
Package
Name
SC16C754IB80
SC16C754IA68
LQFP80
PLCC68
Description
plastic low profile quad flat package; 80 leads; body 12
×
12
×
1.4 mm
plastic leaded chip carrier; 68 leads
Version
SOT315-1
SOT188-2
Type number
9397 750 11618
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 19 June 2003
2 of 49
Philips Semiconductors
SC16C754
Quad UART with 64-byte FIFO
65 INTSEL
GND
handbook, full pagewidth
61 CDD
CDA
63 RXD
64 VCC
RXA
62 RID
RIA
D7
D6
D5
D4
D3
68 D2
67 D1
66 D0
9
8
7
6
5
4
3
2
1
DSRA 10
CTSA 11
DTRA 12
VCC 13
RTSA 14
INTA 15
CSA 16
TXA 17
IOW 18
TXB 19
CSB 20
INTB 21
RTSB 22
GND 23
DTRB 24
CTSB 25
DSRB 26
60 DSRD
59 CDSD
58 DTRD
57 GND
56 RTSD
55 INTD
54 CSD
53 TXD
SC16C754IA68
52 IOR
51 TXC
50 CSC
49 INTC
48 RTSC
47 VCC
46 DTRC
45 CTSC
44 DSRC
CDB 27
RIB 28
RXB 29
CLKSEL 30
NC 31
A2 32
A1 33
A0 34
XTAL1 35
XTAL2 36
RESET 37
RXRDY 38
TXRDY 39
GND 40
RXC 41
RIC 42
CDC 43
002aaa367
Fig 3. PLCC68 pin configuration.
5.2 Pin description
Table 2:
Symbol
A0
A1
A2
CDA, CDB,
CDC, CDD
Pin description
Pin
LQFP80 PLCC68
30
29
28
79, 23,
39, 63
34
33
32
9, 27,
43, 61
I
I
I
I
Address 0 select bit.
Internal registers address selection.
Address 1 select bit.
Internal registers address selection.
Address 2 select bit.
Internal registers address selection.
Carrier Detect (Active-LOW).
These inputs are associated with individual
UART channels A through D. A logic LOW on these pins indicates that a
carrier has been detected by the modem for that channel. The state of these
inputs is reflected in the modem status register (MSR).
Type
Description
9397 750 11618
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 19 June 2003
5 of 49