ADCLK946BCPZ datasheet, PDF - EEWORLD Datasheet

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ADCLK946BCPZ: DescriptionClock Fanout Buffer 6-OUT 1-IN 1:6 Medical 24-Pin LFCSP EP Tray; File Size274KB，13 Pages; ManufacturerADI; Websitehttps://www.analog.com

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ADCLK946BCPZ Overview

Clock Fanout Buffer 6-OUT 1-IN 1:6 Medical 24-Pin LFCSP EP Tray

ADCLK946BCPZ Parametric

Parameter Name	Attribute value
EU restricts the use of certain hazardous substances	Compliant
ECCN (US)	EAR99
Part Status	Active
HTS	8542.39.00.01
Type	Fanout Buffer
Fanout	1:6
Number of Outputs per Chip	6
Maximum Propagation Delay Time @ Maximum CL (ns)	0.22@3.3V
Absolute Propagation Delay Time (ns)	0.22
Input Logic Level	CML\|CMOS\|LVDS\|LVPECL
Output Logic Level	LVPECL
Minimum Operating Supply Voltage (V)	-2.97\|2.97
Typical Operating Supply Voltage (V)	-3.3\|3.3
Maximum Operating Supply Voltage (V)	-3.63\|3.63
Minimum Operating Temperature (°C)	-40
Maximum Operating Temperature (°C)	85
Supplier Temperature Grade	Industrial
Packaging	Tray
Pin Count	24
Standard Package Name	CSP
Supplier Package	LFCSP EP
Mounting	Surface Mount
Package Height	0.73
Package Length	4
Package Width	4
PCB changed	24
Lead Shape	No Lead

User Manual

【User Guides】UG-069: Setting Up the Evaluation Board for the ADCLK946

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Data Sheet

FEATURES

4.8 GHz operating frequency

75 fs rms broadband random jitter

On-chip input terminations

3.3 V power supply

Six LVPECL Outputs,

SiGe Clock Fanout Buffer

ADCLK946

FUNCTIONAL BLOCK DIAGRAM

ADCLK946

LVPECL

REF

CLK

08053-001

REFERENCE

APPLICATIONS

Low jitter clock distribution

Clock and data signal restoration

Level translation

Wireless communications

Wired communications

Medical and industrial imaging

ATE and high performance instrumentation

GENERAL DESCRIPTION

The

ADCLK946

is an ultrafast clock fanout buffer fabricated on

the Analog Devices, Inc., proprietary XFCB3 silicon germanium

(SiGe) bipolar process. This device is designed for high speed

applications requiring low jitter.

The device has a differential input equipped with center-tapped,

differential, 100 Ω on-chip termination resistors. The input accepts

dc-coupled LVPECL, CML, 3.3 V CMOS (single ended), and

ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A V

REF

is available for biasing ac-coupled inputs.

The

ADCLK946

features six full-swing emitter-coupled logic

(ECL) output drivers. For LVPECL (positive ECL) operation,

bias V

to the positive supply and V

to ground. For ECL

operation, bias V

to ground and V

to the negative supply.

The ECL output stages are designed to directly drive 800 mV

each side into 50 Ω terminated to V

− 2 V for a total differen-

tial output swing of 1.6 V.

The

ADCLK946

is available in a 24-lead LFCSP and is specified

for operation over the standard industrial temperature range of

−40°C to +85°C.

Figure 1.

Rev. B

Document Feedback

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

ADCLK946

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics ............................................................. 3

Absolute Maximum Ratings ............................................................ 5

Determining Junction Temperature .......................................... 5

ESD Caution .................................................................................. 5

Data Sheet

Thermal Performance ...................................................................5

Pin Configuration and Function Descriptions..............................6

Typical Performance Characteristics ..............................................7

Functional Description .....................................................................9

Clock Inputs ...................................................................................9

Clock Outputs ................................................................................9

PCB Layout Considerations ...................................................... 10

Input Termination Options ....................................................... 11

Outline Dimensions ....................................................................... 12

Ordering Guide .......................................................................... 12

REVISION HISTORY

8/2017—Rev. A to Rev. B

Changes to Figure 2 .......................................................................... 6

Updated Outline Dimensions ....................................................... 12

Changes to Ordering Guide .......................................................... 12

5/2010—Rev. 0 to Rev. A

Changes to Table 1, DC Output Characteristics ...........................3

4/2009—Revision 0: Initial Version

Rev. B | Page 2 of 12

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