N-series Intel
®
Pentium
®
Processors
and Intel
®
Celeron
®
Processors
Datasheet – Volume 1 of 3
February 2016
Document Number: 332092-002
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Intel, Celeron, Pentium, Intel
®
Seamless Display Refresh Rate Switching Technology (Intel
®
SDRRS Technology), Intel
®
Display Power Saving
Technology (Intel
®
DPST), Intel
®
Trusted Execution Engine (Intel
®
TXE), Intel
®
Virtualization Technology (Intel
®
VT), Intel
®
Virtualization Technology
(Intel
®
VT) for IA-32, Intel
®
64 and Intel
®
Architecture (Intel
®
VT-x), Enhanced Intel SpeedStep
®
Technology, Intel
®
Display Power Saving Technology
(Intel
®
DPST), Intel
®
Automatic Display Brightness, Intel
®
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®
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Copyright © 2015-2016, Intel Corporation
L
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Datasheet, Volume 1 of 3
Contents
1
Introduction
............................................................................................................. 17
1.1
Document Structure and Scope ......................................................................... 19
1.2
Terminology ................................................................................................... 20
1.3
Feature Overview ............................................................................................ 22
1.4
Related Documents.......................................................................................... 26
Physical Interfaces
................................................................................................... 27
2.1
Platform Power Rails ........................................................................................ 27
2.2
SoC Physical Signal Per Interface....................................................................... 29
2.2.1
System Memory Controller Interface Signals (DDR3L) .............................. 29
2.2.2
USB 2.0 Controller Interface Signals ...................................................... 30
2.2.3
USB 3.0 Interface Signals ..................................................................... 31
2.2.4
Integrated Clock Interface Signals ......................................................... 31
2.2.5
Display—Digital Display Interface (DDI) Signals....................................... 32
2.2.6
MIPI*-CSI (Camera Serial Interface) and ISP Interface Signals.................. 33
2.2.7
Storage Controller Interface Signals....................................................... 33
2.2.8
High Speed UART Interface Signals........................................................ 34
2.2.9
I
2
C Interface Signals............................................................................ 35
2.3
SIO—Serial Peripheral Interface (SPI) Signals ..................................................... 35
2.3.1
PCU—Fast Serial Peripheral Interface (SPI) Signals .................................. 36
2.3.2
PCU—Real Time Clock (RTC) Interface Signals......................................... 36
2.3.3
PCU—Low Pin Count (LPC) Bridge Interface Signals.................................. 36
2.3.4
JTAG Interface Signals ......................................................................... 37
2.3.5
PCI Express* (PCIe*) Signals................................................................ 37
2.3.6
SATA Signals ...................................................................................... 38
2.3.7
SMBus Signals .................................................................................... 38
2.3.8
Intel
®
High Definition Audio (Intel
®
HD Audio) Signals ............................. 38
2.3.9
Power Management Unit (PMU) Signals .................................................. 39
2.3.10
Speaker Signals .................................................................................. 39
2.3.11
Miscellaneous Signals........................................................................... 40
2.4
Hardware Straps ............................................................................................. 40
2.5
GPIO Multiplexing ............................................................................................ 42
Processor Core..........................................................................................................
49
3.1
SoC Transaction Router .................................................................................... 49
3.2
Intel
®
Virtualization Technology (Intel
®
VT)........................................................ 49
3.2.1
Intel
®
VT-x Objectives ......................................................................... 49
3.2.2
Intel
®
VT-x Features ........................................................................... 50
3.3
Security and Cryptography Technologies............................................................. 50
3.3.1
PCLMULQDQ Instruction ....................................................................... 50
3.3.2
Digital Random Number Generator ........................................................ 51
3.3.3
Power Aware Interrupt Routing ............................................................. 51
3.4
Platform Identification and CPUID ...................................................................... 51
3.5
References ..................................................................................................... 51
Integrated Clock
....................................................................................................... 53
Thermal Management
............................................................................................... 55
5.1
Overview........................................................................................................ 55
5.2
Digital Thermal Sensors.................................................................................... 55
5.2.1
DTS Timing ........................................................................................ 56
5.3
Hardware Trips................................................................................................ 57
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3
4
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Datasheet, Volume 1 of 3
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5.4
5.5
5.6
5.7
6
5.3.1
Catastrophic Trip (THERMTRIP).............................................................
SoC Programmable Trips..................................................................................
5.4.1
Aux3 Trip ..........................................................................................
5.4.2
Aux2, Aux1, Aux0 Trip.........................................................................
Platform Trips.................................................................................................
5.5.1
PROCHOT# ........................................................................................
5.5.2
EXTTS ...............................................................................................
5.5.3
SVID.................................................................................................
Dynamic Platform Thermal Framework (DPTF) ....................................................
Thermal Status ...............................................................................................
57
57
58
58
58
58
58
58
58
58
Power Management..................................................................................................
59
6.1
Power Management Features ............................................................................ 59
6.2
Power Management States Supported ................................................................ 59
6.2.1
System States.................................................................................... 59
6.2.2
Integrated Memory Controller States ..................................................... 62
6.3
Processor Core Power Management ................................................................... 62
6.3.1
Enhanced Intel
®
SpeedStep
®
Technology .............................................. 62
6.3.2
Dynamic Cache Sizing ......................................................................... 62
6.3.3
Low-Power Idle States......................................................................... 63
6.3.3.1 Clock Control and Low-Power States ........................................... 63
6.3.4
Processor Core C-States Description ...................................................... 64
6.3.4.1 Core C0 State .......................................................................... 64
6.3.4.2 Core C1/C1E State ................................................................... 64
6.3.4.3 Core C6 State .......................................................................... 64
6.3.4.4 Core C7 State .......................................................................... 64
6.3.4.5 C-State Auto-Demotion ............................................................. 65
6.3.5
Package C-States................................................................................ 65
6.3.5.1 Package C0 State ..................................................................... 66
6.3.5.2 Package C1/C1E State .............................................................. 66
6.3.5.3 Package C6 State ..................................................................... 66
6.3.5.4 Package C7 State ..................................................................... 67
6.3.6
Graphics and Video Decoder C-State ..................................................... 67
6.3.7
Intel
®
Display Power Saving Technology (Intel
®
DPST)............................ 67
6.3.8
Intel
®
Automatic Display Brightness...................................................... 67
6.3.9
Intel
®
Seamless Display Refresh Rate Switching Technology (Intel
®
SDRRS Technology) ............................................................................ 68
6.4
Memory Power Management............................................................................. 68
6.4.1
Disabling Unused System Memory Outputs............................................. 68
6.4.2
DRAM Power Management and Initialization ........................................... 68
6.4.2.1 Initialization Role of CKE ........................................................... 68
6.4.2.2 Conditional Self-Refresh ............................................................ 69
6.4.2.3 Dynamic Power-Down Operation ................................................ 69
6.4.2.4 DRAM I/O Power Management ................................................... 69
System Memory Controller
....................................................................................... 71
7.1
DDR3L Interface Signals .................................................................................. 71
7.2
System Memory Technology Supported.............................................................. 72
Graphics, Video, and Display
....................................................................................
8.1
SoC Graphics Display.......................................................................................
8.1.1
Primary Display Planes A, B, and C........................................................
8.1.1.1 Video Sprite Planes A, B, C, D, E, and F.......................................
8.1.1.2 Cursors A, B, and C ..................................................................
8.1.2
Display Pipes......................................................................................
8.1.3
Display Physical Interfaces ...................................................................
8.2
Digital Display Interfaces .................................................................................
73
73
73
73
74
74
74
74
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Datasheet, Volume 1 of 3
8.2.1
8.3
8.4
9
High Definition Multi-media Interface (HDMI) .......................................... 75
8.2.1.1 DisplayPort*............................................................................. 76
8.2.1.2 embedded DisplayPort* (eDP*)................................................... 77
8.2.1.3 DisplayPort* Auxiliary Channel.................................................... 77
8.2.1.4 Hot-Plug Detect (HPD) ............................................................... 77
8.2.1.5 Integrated Audio Over HDMI and DisplayPort* .............................. 77
8.2.1.6 High-Bandwidth Digital Content Protection (HDCP) ........................ 77
3-D Graphics and Video.................................................................................... 77
8.3.1
Features ............................................................................................ 78
8.3.2
3-D Engine Execution Units................................................................... 78
8.3.3
3-D Pipeline........................................................................................ 78
8.3.3.1 Vertex Fetch (VF) Stage............................................................. 78
8.3.3.2 Vertex Shader (VS) Stage .......................................................... 79
8.3.3.3 Geometry Shader (GS) Stage ..................................................... 79
8.3.3.4 Clip Stage ................................................................................ 79
8.3.3.5 Strips and Fans (SF) Stage......................................................... 79
8.3.3.6 Windower/IZ (WIZ) Stage .......................................................... 79
VED (Video Encode/Decode) ............................................................................. 79
8.4.1
Features ............................................................................................ 80
MIPI*-CSI (Camera Serial Interface) and ISP...........................................................
83
9.1
Signal Descriptions .......................................................................................... 83
9.1.1
Imaging Capabilities ............................................................................ 84
9.1.2
Simultaneous Acquisition...................................................................... 84
9.1.3
Primary Camera Still Image Resolution................................................... 85
9.1.4
Burst Mode Support ............................................................................. 85
9.1.5
Continuous Mode Capture..................................................................... 85
9.1.6
Secondary Camera Still Image Resolution ............................................... 85
9.1.7
Primary Camera Video Resolution .......................................................... 85
9.1.8
Secondary Camera Video Resolution ...................................................... 85
9.1.9
Bit Depth ........................................................................................... 85
9.2
Imaging Subsystem Integration......................................................................... 86
9.2.1
Processor Core.................................................................................... 86
9.2.2
Imaging Signal Processor (ISP) ............................................................. 86
9.2.2.1 MIPI*-CSI-2 Ports..................................................................... 86
9.2.2.2 I
2
C for Camera Interface............................................................ 87
9.2.2.3 Camera Sideband for Camera Interface........................................ 87
9.3
Functional Description ...................................................................................... 88
9.3.1
Preview Mode ..................................................................................... 88
9.3.2
Image Capture.................................................................................... 88
9.3.3
Video Capture ..................................................................................... 88
9.3.4
ISP Overview ...................................................................................... 88
9.4
MIPI*-CSI-2 Receiver....................................................................................... 89
9.4.1
MIPI*-CSI-2 Receiver Features ............................................................. 90
SoC Storage
.............................................................................................................. 93
10.1
SoC Storage Overview ..................................................................................... 93
10.1.1
Storage Control Cluster (e-MMC*, SDIO, SD) .......................................... 93
10.2
Signal Descriptions .......................................................................................... 93
10.3
References ..................................................................................................... 94
USB Controller Interfaces
......................................................................................... 95
11.1
SoC Supports.................................................................................................. 95
11.2
Signal Descriptions .......................................................................................... 96
11.3
USB 3.0 xHCI (Extensible Host Controller Interface) ............................................. 97
11.3.1
Features of USB 3.0 Host ..................................................................... 97
11.3.1.1 USB 3.0 Features ...................................................................... 97
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Datasheet, Volume 1 of 3
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