CD4541BC Programmable Timer
October 1987
Revised May 2002
CD4541BC
Programmable Timer
General Description
The CD4541BC Programmable Timer is designed with a
16-stage binary counter, an integrated oscillator for use
with an external capacitor and two resistors, output control
logic, and a special power-on reset circuit. The special fea-
tures of the power-on reset circuit are first, no additional
static power consumption and second, the part functions
across the full voltage range (3V–15V) whether power-on
reset is enabled or disabled.
Timing and the counter are initialized by turning on power,
if the power-on reset is enabled. When the power is
already on, an external reset pulse will also initialize the
timing and counter. After either reset is accomplished, the
oscillator frequency is determined by the external RC net-
work. The 16-stage counter divides the oscillator frequency
by any of 4 digitally controlled division ratios.
Features
s
Available division ratios 2
8
, 2
10
, 2
13
, or 2
16
s
Increments on positive edge clock transitions
s
Built-in low power RC oscillator (
±
2% accuracy over
temperature range and
±
10% supply and
±
3% over pro-
cessing @
<
10 kHz)
s
Oscillator frequency range
≈
DC to 100 kHz
s
Oscillator may be bypassed if external clock is available
(apply external clock to pin 3)
s
Automatic reset initializes all counters when power turns
on
s
External master reset totally independent of automatic
reset operation
s
Operates at 2
n
frequency divider or single transition
timer
s
Q/Q select provides output logic level flexibility
s
Reset (auto or master) disables oscillator during reset-
ting to provide no active power dissipation
s
Clock conditioning circuit permits operation with very
slow clock rise and fall times
s
Wide supply voltage range—3.0V to 15V
s
High noise immunity—0.45 V
DD
(typ.)
s
5V–10V–15V parameter ratings
s
Symmetrical output characteristics
s
Maximum input leakage 1
µ
A at 15V over full tempera-
ture range
s
High output drive (pin 8) min. one TTL load
Ordering Code:
Order Number
CD4541BCM
CD4541BCN
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
N.C.—Not connected
Top View
© 2002 Fairchild Semiconductor Corporation
DS006001
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CD4541BC
Truth Table
Pin
0
5
6
9
10
Auto Reset Operating
Timer Operational
Output Initially Low
after Reset
Single Cycle Mode
State
1
Auto Reset Disabled
Master Reset On
Output Initially High
after Reset
Recycle Mode
Division Ratio Table
Number of
A
B
Counter Stages
n
0
0
1
1
0
1
0
1
13
10
8
16
8192
1024
256
65536
Count
2
n
Operating Characteristics
With Auto Reset pin set to a “0” the counter circuit is initial-
ized by turning on power. Or with power already on, the
counter circuit is reset when the Master Reset pin is set to
a “1”. Both types of reset will result in synchronously reset-
ting all counter stages independent of counter state.
The RC oscillator frequency is determined by the external
RC network, i.e.:
However, when B is “0”, normal counting is interrupted and
the 9th counter stage receives its clock directly from the
oscillator (i.e., effectively outputting 2
8
).
The Q/Q select output control pin provides for a choice of
output level. When the counter is in a reset condition and
Q/Q select pin is set to a “0” the Q output is a “0”. Corre-
spondingly, when Q/Q select pin is set to a “1” the Q output
is a “1”.
When the mode control pin is set to a “1”, the selected
count is continually transmitted to the output. But, with
mode pin “0” and after a reset condition the RS flip-flop
resets (see Logic Diagram), counting commences and after
2
n−1
counts the RS flip-flop sets which causes the output to
change state. Hence, after another 2
n−1
counts the output
will not change. Thus, a Master Reset pulse must be
applied or a change in the mode pin level is required to
reset the single cycle operation.
and R
S
≈
2 R
tc
where R
S
≥
10 k
Ω
The time select inputs (A and B) provide a two-bit address
to output any one of four counter stages (2
8
, 2
10
, 2
13
, and
2
16
). The 2
n
counts as shown in the Division Ratio Table
represent the Q output of the Nth stage of the counter.
When A is “1”, 2
16
is selected for both states of B.
Typical RC Oscillator
Characteristics
RC Oscillator Frequency as a
Function of R
TC
and C
Solid Line
=
R
TC
=
56 kΩ, R
S
=
1 kΩ and C
=
1000 pF
f
=
10.2 kHz @ V
DD
=
10V and T
A
=
25°
Dashed Line
=
R
TC
=
56 kΩ, R
S
=
120 kΩ and C
=
1000 pF
f
=
7.75 kHz @ V
DD
=
10V and T
A
=
25°
Line A: f as a function of C and (R
TC
=
56 kΩ; R
S
=
120k
Line B: f as a function of R
TC
and (C
=
100 pF; R
S
=
2 R
TC
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2
CD4541BC
Operating Characteristics
(Continued)
Oscillator Circuit Using RC Configuration
Logic Diagram
V
DD
=
Pin 14
V
SS
=
Pin 7
3
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CD4541BC
Absolute Maximum Ratings
(Note 1)
(Note 2)
Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Storage Temperature Range (T
S
)
Power Dissipation (P
D
)
Dual-In-Line
Small Outline
Lead Temperature (T
L
)
(soldering, 10 seconds)
260
°
C
(Note 2)
700 mW
500 mW
Recommended Operating
Conditions
(Note 2)
Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Operating Temperature Range
3V to 15V
0 to V
DD
−
0.5V to
+
18V
−
0.5V to V
DD
+
0.5V
−
65
°
C to
+
150
°
C
−
55
°
C to
+
125
°
C
Note 1:
“Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device operation.
Note 2:
V
SS
=
0V unless otherwise specified.
DC Electrical Characteristics
Symbol
I
DD
Parameter
Quiescent Device Current
Conditions
V
DD
=
5V, V
IN
=
V
DD
or V
SS
V
DD
=
10V, V
IN
=
V
DD
or V
SS
V
DD
=
15V, V
IN
=
V
DD
or V
SS
−55°C
Min
Max
5
10
20
0.05
0.05
0.05
4.95
4.95
9.95
14.95
1.5
3.0
4.0
3.5
7.0
11.0
2.85
4.16
19.3
7.96
4.19
16.3
−0.1
0.1
3.5
7.0
11.0
2.27
4.0
15.6
6.42
3.38
13.2
Min
+25°C
Typ
0.005
0.010
0.015
0
0
0
5
10
15
2
4
6
3
6
9
3.6
9.0
34.0
130
8.0
30.0
−10
−
5
10
−
5
−0.1
0.1
1.5
3.0
4.0
Max
5
10
20
0.05
0.05
0.05
+125°C
Min
Max
150
300
600
0.05
0.05
0.05
4.95
9.95
14.95
1.5
3.0
4.0
3.5
7.0
11.0
1.6
2.8
10.9
4.49
2.37
9.24
−1.0
1.0
Units
µA
V
OL
LOW Level Output Voltage
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
|I
O
|
<
1µA
V
V
OH
HIGH Level Output Voltage
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
|I
O
|
<
1
µA
9.95
14.95
V
V
IL
LOW Level Input Voltage
V
DD
=
5V, V
O
=
0.5V or 4.5V
V
DD
=
10V, V
O
=
1.0V or 9.0V
V
DD
=
15V, V
O
=
1.5V or 13.5V
V
V
IH
HIGH Level Input Voltage
V
DD
=
5V, V
O
=
0.5V or 4.5V
V
DD
=
10V, V
O
=
1.0V or 9.0V
V
DD
=
15V, V
O
=
1.5V or 13.5V
V
I
OL
LOW Level Output Current
(Note 3)
V
DD
=
5V, V
O
=
0.4V
V
DD
=
10V, V
O
=
0.5V
V
DD
=
15V, V
O
=
1.5V
V
DD
=
5V, V
O
=
2.5V
V
DD
=
10V, V
O
=
9.5V
V
DD
=
15V, V
O
=
13.5V
V
DD
=
15V, V
IN
=
0V
V
DD
=
15V, V
IN
=
15V
mA
I
OH
HIGH Level Output Current
(Note 3)
mA
I
IN
Input Current
µA
Note 3:
I
OH
and I
OL
are tested one output at a time.
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4
CD4541BC
AC Electrical Characteristics
T
A
=
25
°
C, C
L
=
50 pF (refer to test circuits)
Symbol
t
TLH
Parameter
Output Rise Time
(Note 4)
Conditions
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
Min
Typ
50
30
25
50
30
25
1.8
0.6
0.4
3.2
1.5
1.0
400
200
150
200
100
70
2.5
6.0
8.5
400
200
150
170
75
50
5.0
100
7.5
pF
pF
ns
1.0
3.0
4.0
MHz
ns
Max
200
100
80
200
100
80
4.0
1.5
1.0
8.0
3.0
2.0
µs
µs
ns
ns
Units
t
THL
Output Fall Time
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
t
PLH,
t
PHL
Turn-Off, Turn-On Propagation Delay,
Clock to Q (2
8
Output)
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
t
PHL,
t
PLH
Turn-On, Turn-Off Propagation Delay,
Clock to Q (2
16
Output)
t
WH(CL)
Clock Pulse Width
f
CL
Clock Pulse Frequency
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
t
WH(R)
MR Pulse Width
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
C
I
C
PD
Average Input Capacitance
Power Dissipation Capacitance (Note 5)
Any Input
Note 4:
AC Parameters are guaranteed by DC correlated testing.
Note 5:
C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics application note:
AN-90.
5
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