BLC8G27LS-240AV
Power LDMOS transistor
Rev. 5 — 2 December 2016
Product data sheet
1. Product profile
1.1 General description
240 W LDMOS packaged asymmetric Doherty power transistor for base station
applications at frequencies from 2500 MHz to 2700 MHz.
Table 1.
Typical performance
Typical RF performance at T
case
= 25
C in an asymmetrical Doherty demo board. V
DS
= 28 V;
I
Dq
= 500 mA (main); V
GS(amp)peak
= 0.5 V, unless otherwise specified.
Test signal
1-carrier W-CDMA
[1]
f
(MHz)
2500 to 2690
V
DS
(V)
28
P
L(AV)
(W)
56
G
p
(dB)
14.5
D
(%)
43
ACPR
(dBc)
35
[1]
Test signal: 3GPP test model 1; 64 DPCH; PAR = 7.2 dB at 0.01% probability on CCDF per carrier.
1.2 Features and benefits
Excellent ruggedness
High-efficiency
Low thermal resistance providing excellent thermal stability
Designed for broadband operation (2500 MHz to 2700 MHz)
Asymmetric design to achieve optimum efficiency across the band
Lower output capacitance for improved performance in Doherty applications
Designed for low memory effects providing excellent digital pre-distortion capability
Internally matched for ease of use
Integrated ESD protection
Compliant to Directive 2002/95/EC, regarding Restriction of Hazardous Substances
(RoHS)
1.3 Applications
RF power amplifiers for base stations and multi carrier applications in the 2500 MHz to
2700 MHz frequency range
BLC8G27LS-240AV
Power LDMOS transistor
2. Pinning information
Table 2.
Pin
1
2
3
4
5
6
7
8
9
[1]
Pinning
Simplified outline
6
2
1
7
[1]
Description
drain2 (peak)
drain1 (main)
gate1 (main)
gate2 (peak)
source
video decoupling (main)
n.c.
n.c.
video decoupling (peak)
Connected to flange.
Graphic symbol
9
2
6
3
5
3
7
4
8
4
8
9
1
aaa-009150
3. Ordering information
Table 3.
Ordering information
Package
Name
BLC8G27LS-240AV
-
Description
plastic earless flanged cavity package; 8 leads
Version
SOT1252-1
Type number
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
GS(amp)main
V
GS(amp)peak
T
stg
T
j
[1]
Parameter
drain-source voltage
main amplifier gate-source voltage
peak amplifier gate-source voltage
storage temperature
junction temperature
Conditions
Min
-
0.5
0.5
65
[1]
Max
65
+13
+13
+150
225
Unit
V
V
V
C
C
-
Continuous use at maximum temperature will affect the reliability, for details refer to the online MTF
calculator.
5. Thermal characteristics
Table 5.
R
th(j-c)
Thermal characteristics
Conditions
V
DS
= 28 V; I
Dq
= 500 mA (main);
V
GS(amp)peak
= 0.5 V; T
case
= 80
C;
P
L
= 56 W
Typ
0.3
Unit
K/W
thermal resistance from junction
to case
Symbol Parameter
BLC8G27LS-240AV
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2016. All rights reserved.
Product data sheet
Rev. 5 — 2 December 2016
2 of 15
BLC8G27LS-240AV
Power LDMOS transistor
6. Characteristics
Table 6.
DC characteristics
T
j
= 25
C unless otherwise specified.
Symbol
Parameter
Conditions
Min
65
1.5
1.6
-
-
-
-
-
Typ
-
1.9
2.1
-
30
-
83
Max Unit
-
2.3
2.4
2.8
-
280
135
V
V
V
A
A
nA
S
m
Main device
V
(BR)DSS
drain-source breakdown voltage V
GS
= 0 V; I
D
= 1.8 mA
V
GS(th)
V
GSq
I
DSS
I
DSX
I
GSS
g
fs
R
DS(on)
gate-source threshold voltage
gate-source quiescent voltage
drain leakage current
drain cut-off current
gate leakage current
forward transconductance
V
DS
= 10 V; I
D
= 180 mA
V
DS
= 28 V; I
D
= 540 mA
V
GS
= 0 V; V
DS
= 28 V
V
GS
= V
GS(th)
+ 3.75 V;
V
DS
= 10 V
V
GS
= 11 V; V
DS
= 0 V
V
DS
= 10 V; I
D
= 180 mA
1.63 -
drain-source on-state resistance V
GS
= V
GS(th)
+ 3.75 V;
I
D
= 6.3 A
Peak device
V
(BR)DSS
drain-source breakdown voltage V
GS
= 0 V; I
D
= 2.2 mA
V
GS(th)
V
GSq
I
DSS
I
DSX
I
GSS
g
fs
R
DS(on)
gate-source threshold voltage
gate-source quiescent voltage
drain leakage current
drain cut-off current
gate leakage current
forward transconductance
V
DS
= 10 V; I
D
= 220 mA
V
DS
= 28 V; I
D
= 660 mA
V
GS
= 0 V; V
DS
= 28 V
V
GS
= V
GS(th)
+ 3.75 V;
V
DS
= 10 V
V
GS
= 11 V; V
DS
= 0 V
V
DS
= 10 V; I
D
= 220 mA
65
1.5
1.6
-
-
-
-
-
-
1.9
2.1
-
40
-
68
-
2.3
2.4
2.8
-
28
112
V
V
V
A
A
nA
S
m
1.94 -
drain-source on-state resistance V
GS
= V
GS(th)
+ 3.75 V;
I
D
= 7.7 A
Table 7.
RF characteristics
Test signal: 1-carrier W-CDMA; PAR = 7.2 dB at 0.01 % probability on the CCDF;
3GPP test model 1; 1 to 64 DPCH; f
1
= 2500 MHz; f
2
= 2690 MHz; RF performance at V
DS
= 28 V;
I
Dq
= 500 mA (main); V
GS(amp)peak
= 0.5 V; T
case
= 25
C; unless otherwise specified; in an
asymmetrical Doherty production test circuit in 2500 MHz to 2690 MHz.
Symbol
G
p
RL
in
D
ACPR
Parameter
power gain
input return loss
drain efficiency
adjacent channel power ratio
Conditions
P
L(AV)
= 56 W
P
L(AV)
= 56 W
P
L(AV)
= 56 W
P
L(AV)
= 56 W
Min
12.8
-
32
-
Typ
14
10
37
25
Max
-
6
-
20
Unit
dB
dB
%
dBc
BLC8G27LS-240AV
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2016. All rights reserved.
Product data sheet
Rev. 5 — 2 December 2016
3 of 15
BLC8G27LS-240AV
Power LDMOS transistor
7. Test information
7.1 Ruggedness in class-AB operation
The BLC8G27LS-240AV is capable of withstanding a load mismatch corresponding to
VSWR = 10 : 1 through all phases under the following conditions: V
DS
= 28 V;
I
Dq
= 500 mA (main); V
GS(amp)peak
= V
GS
- 1 V (V
GS
: I
Dq
at 750 mA); P
L
= 200 W (CW);
f = 2500 MHz.
7.2 Impedance information
Table 8.
Typical impedance of main device
Measured load-pull data of main device; I
Dq
= 1000 mA; V
DS
= 28 V. Typical values unless otherwise
specified.
f
(MHz)
2500
2600
2700
2500
2600
2700
[1]
[2]
Z
S[1]
()
2.7
j4.1
2.7
j5.2
2.9
j4.3
2.7
j4.1
2.7
j5.2
2.9
j4.3
Z
L[1]
()
1.0
j4.5
1.0
j4.5
1.0
j4.5
1.7
j3.9
1.5
j3.7
1.4
j4.1
P
L[2]
(W)
197
196
186
159
144
149
D[2]
(%)
53.5
53.5
54.3
62.6
61.2
58.5
G
p[2]
(dB)
13.1
14.1
15.7
15.2
16.5
17.2
Maximum power load
Maximum drain efficiency load
Z
S
and Z
L
defined in
Figure 1.
at 3 dB gain compression.
Table 9.
Typical impedance of peak device
Measured load-pull data of peak device; I
Dq
= 1230 mA; V
DS
= 28 V. Typical values unless otherwise
specified.
f
(MHz)
2500
2600
2700
2500
2600
2700
[1]
[2]
Z
S[1]
()
2.5
j5.6
3.9
j5.1
3.4
j4.2
2.5
j5.6
3.9
j5.1
3.4
j4.2
Z
L[1]
()
2.1
j4.9
2.1 j4.9
2.6
j5.1
2.0
j2.9
1.8 j3.1
1.8
j3.5
P
L[2]
(W)
256
254
240
187
177
174
D[2]
(%)
53.3
53.8
53.3
62.1
60.4
59.5
G
p[2]
(dB)
13.7
14.4
15.9
16.0
16.9
18.1
Maximum power load
Maximum drain efficiency load
Z
S
and Z
L
defined in
Figure 1.
at 3 dB gain compression.
BLC8G27LS-240AV
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2016. All rights reserved.
Product data sheet
Rev. 5 — 2 December 2016
4 of 15
BLC8G27LS-240AV
Power LDMOS transistor
drain
Z
L
gate
Z
S
001aaf059
Fig 1.
Definition of transistor impedance
7.3 VBW in Doherty operation
The BLC8G27LS-240AV shows 110 MHz (typical) video band-width in Doherty demo
board in 2600 MHz at V
DS
= 28 V; I
Dq
= 500 mA and V
GS(amp)peak
= 0.5 V.
7.4 Test circuit
50 mm
50 mm
C1
C21
C2
C8
C9
C10
C11
R2
C3
C13
C12
C14
80 mm
C4
C15
C5
R1
C19
C20
R3
C16 C18
C6
C17
C7
C22
aaa-015170
Printed-Circuit Board (PCB): Rogers RO4350B with a thickness of 0.508 mm.
See
Table 10
for a list of components.
Fig 2.
Component layout
BLC8G27LS-240AV
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2016. All rights reserved.
Product data sheet
Rev. 5 — 2 December 2016
5 of 15
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