Freescale Semiconductor
MPC5642A
Rev. 3.2, 12/2014
MPC5642A Microcontroller
Datasheet
This is the MPC5642A Datasheet set consisting of the following files:
• MPC5642A Datasheet
Addendum (MPC5642A_AD),
Rev. 1
• MPC5642A Datasheet
(MPC5642A),
Rev. 3.1
© Freescale Semiconductor, Inc., 2014. All rights reserved.
Freescale Semiconductor
Datasheet Addendum
MPC5642A_AD
Rev. 1, 12/2014
MPC5642A Microcontroller
Datasheet Addendum
This addendum describes corrections to the
MPC5642A
Microcontroller Datasheet,
order number MPC5642A.
For convenience, the addenda items are grouped by
revision. Please check our website at
http://www.freescale.com/powerarchitecture for the
latest updates.
The current version available of the
MPC5642A
Microcontroller Datasheet
is Revision 3.1.
Table of Contents
1
2
Addendum List for Revision 3.1 . . . . . . . . . . . . . . 2
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . 2
© Freescale Semiconductor, Inc., 2014. All rights reserved.
1
Addendum List for Revision 3.1
Table 1. MPC5642A Rev 3.1 Addendum
Location
Description
In “Temperature Sensor Electrical Characteristics” table, update the Min and Max value of
“Accuracy” parameter to -20
o
C and +20
o
C, respectively.
Section 3.11, “Temperature
Sensor Electrical
Characteristics”,
Page 77
2
Revision History
Table 2. Revision History Table
Rev. Number
1.0
Initial release.
Substantive Changes
Date of Release
12/2014
Table 2
provides a revision history for this datasheet addendum document.
MPC5642A_AD, Rev. 1
2
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Document Number: MPC5642A_AD
Rev. 1
12/2014
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MPC5642A
Rev. 3.1, 06/2012
MPC5642A
Qorivva MPC5642A
Microcontroller Data Sheet
208 MAPBGA
(17 x 17 mm)
176 LQFP
(24 × 24 mm)
324 TEPBGA
(23 × 23 mm)
• 150 MHz e200z4 Power Architecture core
– Variable length instruction encoding (VLE)
– Superscalar architecture with 2 execution units
– Up to 2 integer or floating point instructions per cycle
– Up to 4 multiply and accumulate operations per cycle
• Memory organization
– 2 MB on-chip flash memory with ECC and
read-while-write (RWW)
– 128 KB on-chip SRAM with standby functionality (32
KB) and ECC
– 8 KB instruction cache (with line locking), configurable
as 2- or 4-way
– 14 + 3 KB eTPU code and data RAM
– 4
4 crossbar switch (XBAR)
– 24-entry MMU
• Fail Safe Protection
– 16-entry Memory Protection Unit (MPU)
– CRC unit with 3 submodules
– Junction temperature sensor
• Interrupt
– Configurable interrupt controller (INTC) with
non-maskable interrupt (NMI)
– 64-channel eDMA
• Serial channels
– 3 eSCI modules
– 3 DSPI modules (2 of which support downstream Micro
Second Channel [MSC])
– 3 FlexCAN modules with 64 message buffers each
– 1 FlexRay module (V2.1) up to 10 Mbit/s w/dual or
single channel, 128 message objects, ECC
• 1 eMIOS
– 24 unified channels
• 1 eTPU2 (second generation eTPU)
—32 standard channels
•
•
•
•
•
•
•
•
•
– 1 reaction module (6 channels with 3 outputs per
channel)
2 enhanced queued analog-to-digital converters (eQADCs)
– Forty 12-bit input channels (multiplexed on 2 ADCs);
expandable to 56 channels with external multiplexers
– 6 command queues
– Trigger and DMA support
– 688 ns minimum conversion time
On-chip CAN/SCI Bootstrap loader with Boot Assist
Module (BAM)
Nexus: Class 3+ for core; Class 1 for eTPU
JTAG (5-pin)
Development Trigger Semaphore (DTS)
– EVTO pin for communication with external tool
Clock generation
– On-chip 4–40 MHz main oscillator
– On-chip FMPLL (frequency-modulated phase-locked
loop)
Up to 112 general purpose I/O lines
– Individually programmable as input, output or special
function
– Programmable threshold (hysteresis)
Power reduction modes: slow, stop, and standby
Flexible supply scheme
– 5 V single supply with external ballast
– Multiple external supply: 5 V, 3.3 V, and 1.2 V
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