DISCRETE SEMICONDUCTORS
DATA SHEET
BF909WR
N-channel dual-gate MOS-FET
Product specification
Supersedes data of 1997 Sep 05
2010 Sep 15
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FET
FEATURES
Specially designed for use at 5 V supply voltage
Short channel transistor with high forward transfer
admittance to input capacitance ratio
Low noise gain controlled amplifier up to 1 GHz
Superior cross-modulation performance during AGC.
APPLICATIONS
VHF and UHF applications with 3 to 7 V supply voltage
such as television tuners and professional
communications equipment.
DESCRIPTION
Enhancement type field-effect transistor in a plastic
microminiature SOT343R package. The transistor
consists of an amplifier MOS-FET with source and
substrate interconnected and an internal bias circuit to
ensure good cross-modulation performance during AGC.
CAUTION
The device is supplied in an antistatic package. The
gate-source input must be protected against static
discharge during transport or handling.
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
T
j
y
fs
C
ig1-s
C
rs
F
drain current
total power dissipation
operating junction temperature
forward transfer admittance
input capacitance at gate 1
reverse transfer capacitance
noise figure
f = 1 MHz
f = 800 MHz
PARAMETER
drain-source voltage
CONDITIONS
36
MIN.
43
3.6
30
2
TYP.
handbook, halfpage
BF909WR
PINNING
PIN
1
2
3
4
SYMBOL
s, b
d
g
2
g
1
source
drain
gate 2
gate 1
DESCRIPTION
d
4
3
g
2
g1
2
1
Top view
Marking code:
ME*
MAM192
s,b
* = - : made in Hong Kong
* = p : made in Hong Kong
* = t : made in Malaysia
Fig.1 Simplified outline (SOT343R) and symbol.
MAX.
7
40
280
150
50
4.3
50
2.8
UNIT
V
mA
mW
C
mS
pF
fF
dB
2010 Sep 15
2
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FET
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
V
DS
I
D
I
G1
I
G2
P
tot
T
stg
T
j
Note
1. Device mounted on a printed-circuit board.
PARAMETER
drain-source voltage
drain current
gate 1 current
gate 2 current
total power dissipation
storage temperature range
operating junction temperature
up to T
amb
= 50
C;
see Fig.2;
note 1
CONDITIONS
65
MIN.
7
40
10
10
280
BF909WR
MAX.
V
UNIT
mA
mA
mA
mW
C
C
+150
+150
MLD150
handbook, halfpage
300
Ptot
(mW)
200
100
0
0
50
100
150
200
Tamb (
o
C)
Fig.2 Power derating curve.
2010 Sep 15
3
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FET
THERMAL CHARACTERISTICS
SYMBOL
R
th j-a
R
th j-s
Notes
1. Device mounted on a printed-circuit board.
2. T
s
is the temperature at the soldering point of the source lead.
STATIC CHARACTERISTICS
T
j
= 25
C;
unless otherwise specified.
SYMBOL
V
(BR)G1-SS
V
(BR)G2-SS
V
(F)S-G1
V
(F)S-G2
V
G1-S(th)
V
G2-S(th)
I
DSX
I
G1-SS
I
G2-SS
Note
1. R
G1
connects gate 1 to V
GG
= 5 V.
DYNAMIC CHARACTERISTICS
Common source; T
amb
= 25
C;
V
DS
= 5 V; V
G2-S
= 4 V; I
D
= 15 mA; unless otherwise specified.
SYMBOL
y
fs
C
ig1-s
C
ig2-s
C
os
C
rs
F
PARAMETER
forward transfer admittance
input capacitance at gate 1
input capacitance at gate 2
drain-source capacitance
noise figure
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 800 MHz; G
S
= G
Sopt
; B
S
= B
Sopt
CONDITIONS
pulsed; T
j
= 25
C
MIN.
36
TYP.
43
3.6
2.3
2.3
30
2
PARAMETER
gate 1-source breakdown voltage
gate 2-source breakdown voltage
forward source-gate 1 voltage
forward source-gate 2 voltage
gate 1-source threshold voltage
gate 2-source threshold voltage
drain-source current
gate 1 cut-off current
gate 2 cut-off current
CONDITIONS
V
G2-S
= V
DS
= 0; I
G1-S
= 10 mA
V
G1-S
= V
DS
= 0; I
G2-S
= 10 mA
V
G2-S
= V
DS
= 0; I
S-G1
= 10 mA
V
G1-S
= V
DS
= 0; I
S-G2
= 10 mA
V
G2-S
= 4 V; V
DS
= 5 V; I
D
= 20
A
V
G1-S
= V
DS
= 5 V; I
D
= 20
A
V
G2-S
= 4 V; V
DS
= 5 V; R
G1
= 120 k;
note 1
V
G2-S
= V
DS
= 0; V
G1-S
= 5 V
V
G1-S
= V
DS
= 0; V
G2-S
= 5 V
6
6
0.5
0.5
0.3
0.3
12
MIN.
PARAMETER
thermal resistance from junction to ambient
thermal resistance from junction to soldering point
CONDITIONS
note 1
T
s
= 91
C;
note 2
BF909WR
VALUE
350
210
UNIT
K/W
K/W
MAX.
15
15
1.5
1.5
1
1.2
20
50
50
UNIT
V
V
V
V
V
V
mA
nA
nA
MAX.
50
4.3
3
3
50
2.8
UNIT
mS
pF
pF
pF
fF
dB
reverse transfer capacitance f = 1 MHz
2010 Sep 15
4
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF909WR
MLB937
MLB936
handbook, halfpage
110
30
handbook, halfpage
ID
(mA)
2V
20
V G2 S = 4 V 3 V
2.5 V
Vunw
(dBμV)
100
1.5 V
90
10
1V
80
0
10
20
30
40
50
gain reduction (dB)
0
0
0.4
0.8
1.2
1.6
2.0
V G1 S (V)
V
DS
= 5 V; V
GG
= 5 V; f
w
= 50 MHz.
f
unw
= 60 MHz; T
amb
= 25
C;
R
G1
= 120 k.
Fig.3
Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical
values; see Fig.17.
V
DS
= 5 V.
T
j
= 25
C.
Fig.4 Transfer characteristics; typical values.
MLB938
30
handbook, halfpage
ID
(mA)
20
V G1 S = 1.4 V
handbook, halfpage
200
MLB939
I G1
(μA)
150
V G2 S = 4 V
1.3 V
1.2 V
3.5 V
3V
1.1 V
1.0 V
0.9 V
100
2.5 V
50
10
2V
0
0
2
4
6
8
10
V DS (V)
0
0
1
2
V G1 S (V)
3
V
DS
= 5 V.
V
G2-S
= 4 V.
T
j
= 25
C.
V
DS
= 5 V.
T
j
= 25
C.
Fig.6
Fig.5 Output characteristics; typical values.
Gate 1 current as a function of gate 1
voltage; typical values.
2010 Sep 15
5
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