NB2308AC3D datasheet, PDF - EEWORLD Datasheet

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NB2308AC3D: DescriptionPhase Locked Loops - PLL 3.3V Eight Output; Categorylogic logic; File Size187KB，12 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn

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NB2308AC3D Overview

Phase Locked Loops - PLL 3.3V Eight Output

NB2308AC3D Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	SOIC
package instruction	SOP, SOP16,.25
Contacts	16
Reach Compliance Code	not_compliant
series	2308
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G16
JESD-609 code	e0
length	9.9 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
MaximumI(ol)	0.008 A
Number of functions	1
Number of inverted outputs
Number of terminals	16
Actual output times	8
Maximum operating temperature	70 °C
Minimum operating temperature
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP16,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	240
power supply	3.3 V
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.2 ns
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn80Pb20)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	3.9 mm
minfmax	133.3 MHz
Base Number Matches	1

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NB2308A

3.3 V Zero Delay

Clock Buffer

The NB2308A is a versatile, 3.3 V zero delay buffer designed to

distribute high-

-speed clocks. It is available in a 16 pin package. The

part has an on-

-chip PLL which locks to an input clock presented on

the REF pin. The PLL feedback is required to be driven to FBK pin,

and can be obtained from one of the outputs. The input- -output

-to-

propagation delay is guaranteed to be less than 250 ps, and the

output- -output skew is guaranteed to be less than 200 ps.

-to-

The NB2308A has two banks of four outputs each, which can be

controlled by the select inputs as shown in the Select Input Decoding

Table. If all the output clocks are not required, Bank B can be

three-

-stated. The select input also allows the input clock to be directly

applied to the outputs for chip and system testing purposes.

Multiple NB2308A devices can accept the same input clock and

distribute it. In this case the skew between the outputs of the two

devices is guaranteed to be less than 700 ps.

The NB2308A is available in five different configurations (Refer to

NB2308A Configurations Table). The NB2308AI1 is the base part,

where the output frequencies equal the reference if there is no counter

in the feedback path. The NB2308AI1H is the high-

-drive version of

the - and the rise and fall times on this device are much faster.

-1

The NB2308AI2 allows the user to obtain 2X and 1X frequencies on

each output bank. The exact configuration and output frequencies

depends on which output drives the feedback pin. The NB2308AI3

allows the user to obtain 4X and 2X frequencies on the outputs.

The NB2308AI4 enables the user to obtain 2X clocks on all outputs.

Thus, the part is extremely versatile, and can be used in a variety of

applications.

The NB2308AI5H is a high-

-drive version with REF/2 on both

banks.

Features

http://onsemi.com

MARKING

DIAGRAMS*

SOIC-

-16

D SUFFIX

CASE 751B

XXXXXXXXXG

AWLYWW

TSSOP-

-16

DT SUFFIX

CASE 948F

XXXX

ALYWG

XXXX = Device Code

= Assembly Location

WL, L = Wafer Lot

= Year

WW, W = Work Week

G or

= Pb--Free Package

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.



Zero Input -- Output Propagation Delay, Adjustable by Capacitive



Load on FBK Input

Multiple Configurations - Refer to NB2308A Configurations Table

Input Frequency Range: 15 MHz to 133 MHz

Multiple Low-

-Skew Outputs

Output-

-Output Skew Less than 200 ps

Device-

-Device Skew Less than 700 ps

Two banks of four outputs, three-

-stateable by two select inputs

Less than 200 ps Cycle- -Cycle Jitter

-to-

Available in 16-

-pin SOIC and TSSOP Packages

3.3 V Operation

Guaranteed Across Commercial and Industrial Temperature Ranges

Advanced 0.35

CMOS Technology

These are Pb-

-Free Devices

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 9 of this data sheet.



Semiconductor Components Industries, LLC, 2010

October, 2010 - Rev. 8

Publication Order Number:

NB2308A/D

NB2308AC3D Related Products

	NB2308AC3D	NB2308AC1D	NB2308AI1HDTR2	NB2308AI1D	NB2308AC1DR2G	NB2308AC1HDTG	NB2308AC2D	NB2308AC1HDR2G	NB2308AC4DR2G
Description	Phase Locked Loops - PLL 3.3V Eight Output			Phase Locked Loops - PLL 3.3V Eight Output	Phase Locked Loops - PLL 3.3V Eight Output Zero Delay Buffer	Phase Locked Loops - PLL 3.3V Eight Output Zero Delay Buffer	Phase Locked Loops - PLL 3.3V Eight Output
Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead	Lead free	Lead free	Contains lead	Lead free	Lead free
Is it Rohs certified?	incompatible	incompatible	conform to	incompatible	conform to	conform to	incompatible	conform to	conform to
Parts packaging code	SOIC	SOIC	TSSOP	SOIC	SOIC	TSSOP	SOIC	SOIC	SOIC
package instruction	SOP, SOP16,.25	SOP, SOP16,.25	TSSOP, TSSOP16,.25	SOP, SOP16,.25	SOP, SOP16,.25	TSSOP, TSSOP16,.25	SOP, SOP16,.25	SOP, SOP16,.25	SOP, SOP16,.25
Contacts	16	16	16	16	16	16	16	16	16
Reach Compliance Code	not_compliant	not_compliant	unknown	not_compliant	unknown	unknown	not_compliant	unknown	unknown
series	2308	2308	-	2308	2308	2308	2308	2308	2308
Input adjustment	STANDARD	STANDARD	-	STANDARD	STANDARD	STANDARD	STANDARD	STANDARD	STANDARD
JESD-30 code	R-PDSO-G16	R-PDSO-G16	-	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16
JESD-609 code	e0	e0	-	e0	e3	e4	e0	e3	e3
length	9.9 mm	9.9 mm	-	9.9 mm	9.9 mm	5 mm	9.9 mm	9.9 mm	9.9 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	-	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
MaximumI(ol)	0.008 A	0.008 A	-	0.008 A	0.008 A	0.012 A	0.008 A	0.012 A	0.008 A
Number of functions	1	1	-	1	1	1	1	1	1
Number of terminals	16	16	-	16	16	16	16	16	16
Actual output times	8	8	-	8	8	8	8	8	8
Maximum operating temperature	70 °C	70 °C	-	85 °C	70 °C	70 °C	70 °C	70 °C	70 °C
Output characteristics	3-STATE	3-STATE	-	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP	-	SOP	SOP	TSSOP	SOP	SOP	SOP
Encapsulate equivalent code	SOP16,.25	SOP16,.25	-	SOP16,.25	SOP16,.25	TSSOP16,.25	SOP16,.25	SOP16,.25	SOP16,.25
Package shape	RECTANGULAR	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE	-	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	240	240	-	240	NOT SPECIFIED	NOT SPECIFIED	240	260	NOT SPECIFIED
power supply	3.3 V	3.3 V	-	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.2 ns	0.2 ns	-	0.2 ns	0.2 ns	0.2 ns	0.4 ns	0.2 ns	0.2 ns
Maximum seat height	1.75 mm	1.75 mm	-	1.75 mm	1.75 mm	1.2 mm	1.75 mm	1.75 mm	1.75 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	-	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	-	3 V	3 V	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	-	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	-	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	-	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	-	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn80Pb20)	Tin/Lead (Sn80Pb20)	-	Tin/Lead (Sn80Pb20)	Tin (Sn)	Nickel/Palladium/Gold (Ni/Pd/Au)	Tin/Lead (Sn80Pb20)	Tin (Sn)	Tin (Sn)
Terminal form	GULL WING	GULL WING	-	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	1.27 mm	-	1.27 mm	1.27 mm	0.65 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	-	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	30	30	-	30	NOT SPECIFIED	NOT SPECIFIED	30	40	NOT SPECIFIED
width	3.9 mm	3.9 mm	-	3.9 mm	3.9 mm	4.4 mm	3.9 mm	3.9 mm	3.9 mm
minfmax	133.3 MHz	133.3 MHz	-	133.3 MHz	133.3 MHz	133.3 MHz	133.3 MHz	133.3 MHz	133.3 MHz
Base Number Matches	1	-	-	1	1	1	-	1	-

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