DATASHEET
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
ICS1894-32
Description
The ICS1894-32 is a low-power, physical-layer device
(PHY) that supports the ISO/IEC 10Base-T and
100Base-TX Carrier-Sense Multiple Access/Collision
Detection (CSMA/CD) Ethernet standards, ISO/IEC
8802.3. It is intended for RMII/MII Node applications and
includes the Auto-MDIX feature that automatically corrects
crossover errors in plant wiring.
The ICS1894-32 incorporates Digital-Signal Processing
(DSP) control in its Physical-Medium Dependent (PMD)
sub-layer. As a result, it can transmit and receive data on
unshielded twisted-pair (UTP) category 5 cables with
attenuation in excess of 24 dB at 100MHz.
The ICS1894-32 provides a Serial-Management Interface
for exchanging command and status information with a
Station-Management (STA) entity. The ICS1894-32
Media-Dependent Interface (MDI) can be configured to
provide full-duplex operation at data rates of 10 Mb/s or
100Mb/s.
In addition, the ICS1894-32 includes a programmable LED
and interrupt output function. The LED outputs can be
configured through registers to indicate the occurance of
certain events such as LINK, COLLISION, ACTIVITY, etc.
The purpose of the programmable interrupt output is to
notify the PHY controller device immediately when a certain
event happens instead of having the PHY controller
continuously poll the PHY. The events that could be used to
generate interrupts are: receiver error, Jabber, page
received, parallel detect fault, link partner acknowledge, link
status change, auto-negotiation complete, remote fault,
collision, etc.
The ICS1894-32 has deep power modes that can result in
significant power savings when the link is broken.
Applications:
NIC cards, PC motherboards, switches,
routers, DSL and cable modems, game machines, printers,
network connected appliances, and industrial equipment.
Features
•
Supports category 5 cables and above with attenuation in
excess of 24dB at 100 MHz.
•
Single-chip, fully integrated PHY provides PCS, PMA,
PMD, and AUTONEG sub layers functions of IEEE
standard.
•
10Base-T and 100Base-TX ISO/IEC 8802.3 compliant
•
MIIM (MDC/MDIO) management bus for PHY register
configuration
•
RMII interface support with external 50 MHz system clock
•
Single 3.3V power supply
•
Highly configurable, supports:
– Media Independent Interface (MII)
– Auto-Negotiation with Parallel detection
– Node applications, managed or unmanaged
– 10M or 100M full duplex modes
*
– Loopback mode for Diagnostic Functions
•
•
•
•
•
•
•
Auto-MDI/MDIX crossover correction
Low-power CMOS (typically 300 mW)
Power-Down mode (typically 21mW)
Clock and crystal supported in MII mode
Programmable LEDs
Interrupt output pin
Fully integrated, DSP-based PMD includes:
– Adaptive equalization and baseline-wander
correction
– Transmit wave shaping and stream cipher
scrambler
– MLT-3 encoder and NRZ/NRZI encoder
•
•
•
•
•
Core power supply (3.3 V)
3.3 V/1.8 V VDDIO operation supported
Smart power control with deep power down feature
Available in 32-pin (5mm x 5mm) QFN package, Pb-free
Available in Industrial Temp and Lead Free
*
For full/half duplex
RMII
only interface support, please refer to ICS1894-33 datasheet.
*
For full/half duplex
MII
only interface support, please refer to ICS1894-34 datasheet.
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
1
ICS1894-32
REV M 021512
ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Block Diagram
100Base-T
10/100 MII/RMII
MAC
Interface
Interface
MUX
PCS
• Framer
• Parallel to Serial
• 4B/5B
PMA
• Clock Recovery
• Link Monitor
• Signal Detection
• Error Detection
TP_PMD
• MLT-3
• Stream Cipher
• Adaptive Equalizer
• Baseline Wander
Correction
Integrated
Switch
10Base-T
MII
Extended
Register
Set
Low-Jitter
Clock
Synthesizer
Clock
Smart Power
Control
Block
Power
Twisted-
Pair
Interface to
Magnetics
Modules and
RJ45
Connector
MII
Management
Interface
Configuration
and Status
Auto-
Negotiation
LEDs and PHY
Address
Pin Assignment
P1/ISO/LED1
P0/LED0
REFOUT
REFIN
TP_AP
TP_AN
VSS
VDD
TP_BN
TP_BP
VDD
TCSR
1
25
VDDD
TXD2
TXD1
TXD3
TXD0
TXEN
SPEED/TXCLK
NLG32 With Ground
Connecting to Thermal Pad
NOD/RXER
ANSEL/RXCLK
VDDIO
RMII/RXDV
9
17
FDPX/RXD0
VSS
MDC
AMDIX/RXD3
RESET_N
P2/INT
MDIO
P3/RXD2
32-pin 5mm x 5mm QFN
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
RXTR1RXD1
2
ICS1894-32
REV M 021512
ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Pin
Name
TP_AP
TP_AN
VSS
VDD
TP_BN
TP_BP
VDD
TCSR
VSS
RESET_N
P2/INT
MDIO
MDC
AMDIX/RXD3
P3/RXD2
RXTRI/
RXD1
FDPX/
RXD0
RMII/RXDV
VDDIO
ANSEL/
RXCLK
NOD/
RXER
SPEED/
TXCLK
TXEN
TXD0
VDDD
TXD1
TXT2
TXD3
REFOUT
REFIN
Pin
Type
1
AIO
AIO
Power
AIO
AIO
Power
AIO
Pin Description
Twisted pair port A (for either transmit or receive) positive signal
Twisted pair port A (for either transmit or receive) negative signal
3.3V Power Supply
Twisted pair port B (for either transmit or receive) negative signal
Twisted pair port B (for either transmit or receive) positive signal
3.3V Power Supply
Transmit Current bias pin, connected to Vdd and ground via resistors (see
“Recommended Component Values” table and the “ICS1894-32 TCSR” figure).
Hardware reset for the entire chip (active low)
PHY address Bit 2 as input (during power on reset/hardware reset)
Interrupt output as output (default active low, can be programmed to active high)
Management Data Input/Output
Management Data Clock
AMDIX enable as input (during power on reset/hardware reset)
Receive data Bit 3 in MII mode as output.
PHY address Bit 3 as input (during power on reset/hardware reset)
Receive data Bit 2 in MII mode as output.
RX tri-state enable as input (during power on reset/hardware reset)
Receive data Bit 1 in both RMII and MII mode as output.
Full duplex enable as input (during power on reset/hardware reset)
Receive data Bit 0 in both RMII and MII mode as output
RMII/MII select as input (during power on reset/hardware reset)
Receive data valid in MII mode and CRS_DV in RMII mode as output.
3.3 V/1.8 V IO Power Supply.
Auto-negotiation enable as input (during power on reset/hardware reset)
Receive clock in MII mode as output.
Node select as input (during power on reset/hardware reset)
Receive error in MII/RMII mode as output
It is recommended to always pull this pin low on power-up or hardware reset.
10M/100M select as input (during power on reset/hardware reset)
Transmit clock in MII mode as output
Transmit enable in RMII/MII mode
Transmit data Bit 0 in RMII/MII mode
3.3 V Power Supply
Transmit data Bit 1 in RMII/MII mode
Transmit data Bit 2 in MII mode
Transmit data Bit 3 in MII mode
25 MHz crystal (or clock) input in MII mode. 50 MHz clock input in RMII mode.
Ground Connect to ground.
Ground Connect to ground.
Input
IO/Ipd
IO
Input
IO/Ipu
IO/Ipd
IO/Ipd
IO/Ipu
IO/Ipd
Power
IO/Ipu
IO/Ipd
22
23
24
25
26
27
28
29
30
IO/Ipu
Input
Input
Power
Input
Input
Input
Input
Output 25 MHz crystal output, floating in RMII mode
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
3
ICS1894-32
REV M 021512
ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Pin
Number
31
32
Pin
Name
P0/LED0
P1/ISO/LED1
Pin
Type
1
IO
IO
Pin Description
PHY address Bit 0 as input (during power on reset/hardware reset) and LED # 0
(function configurable, default is "activity/no activity") as output
PHY address Bit 1 as input (during power on reset/hardware reset) and LED # 1
(function configurable, default is "10/100 mode") as output; After latch, alternates as
a real time receiver isolation input.
PADDLE
Notes:
VSS
Ground Connect to ground.
1. AIO: Analog input/output PAD.
IO: Digital input/output.
IN/Ipu: Digital input with internal 20k pull-up.
IN/Ipd: Digital input with internal 20k pull-down.
IO/Ipu: Digital input/output with internal 20k pull-up.
IO/Ipd: Digital input/output with internal 20k pull-down.
2. MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents
valid data to MAC on the MII interface. RXD[3..0] is invalid when RXDV is de-asserted.
3. RMII Rx Mode: The RXD[1:0] bits are synchronous with REFIN. For each clock period in which CRS_DV is
asserted, two bits of recovered data are sent from the PHY to the MAC.
4. MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid
data from the MAC on the MII interface. TXD[3..0] has no effect when TXEN is de-asserted.
5. RMII Tx Mode: The TXD[1:0] bits are synchronous with REFIN. For each clock period in which TX_EN is
asserted, two bits of data are received by the PHY from the MAC.
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
4
ICS1894-32
REV M 021512
ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Strapping Options
Pin
Number
14
15
11
31
32
16
17
Pin
Name
AMDIX/RXD3
P3/RXD2
P2/INT
P0/LED0
P1/ISO/LED1
RXTRI/RXD1
FDPX/RXD0
Pin
Type
1
IO/Ipu
IO/Ipd
IO/Ipd
IO
IO
IO/Ipd
IO/Ipu
1 = AMDIX enable
0 = AMDIX disable
Pin Function
The PHY address is set by P[3:0] at power-on reset. P0 and P1 must have external
pull-up or pull-down to set address at start up.
1 = Real time receiver isolation function enable
3
; 0 = Receiver Tristate Disable
1=Full duplex
0=Half duplex (mode not supported)
Ignored if Auto negotiation is enabled
1 = RMII mode
0 = MII mode
1=Enable auto negotiation
0=Disable auto negotiation
0=Node mode
1=repeater mode (mode not supported)
1=100M mode
0=10M mode
Ignored if Auto negotiation is enabled
18
20
21
22
RMII/RXDV
ANSEL/RXCLK
NOD/RXER
SPEED/TXCLK
IO/Ipd
IO/Ipu
IO/Ipd
IO/Ipu
1.
IO/Ipu = Digital Input with internal 20k pull-up during power on reset/hardware reset; output pin otherwise.
2.
IO/Ipd = Digital Input with internal 20k pull-down during power on reset/hardware reset; output pin otherwise.
3. If RXTRI/RXD1 pin is latched high during power on reset/hardware reset, P1/ISO/LED1 functions as RX real time
isolation control input after latch and LED1 function will be disabled.
Functional Description
The ICS1894-32 is an ethernet PHYceiver. During data
transmission, it accepts sequential nibbles/di-bits from the
MAC (Media Access Control), converts them into a serial bit
stream, encodes them, and transmits them over the medium
through an external isolation transformer. When receiving
data, the ICS1894-32 converts and decodes a serial bit
stream (acquired from an isolation transformer that
interfaces with the medium) into sequential nibbles/di-bits. It
subsequently presents these nibbles/di-bits to the MAC
Interface.
The ICS1894-32 implements the OSI model’s physical
layer, consisting of the following, as defined by the ISO/IEC
8802-3 standard:
•
•
•
•
Physical Coding sublayer (PCS)
Physical Medium Attachment sublayer (PMA)
Physical Medium Dependent sublayer (PMD)
Auto-Negotiation sublayer
The ICS1894-32 is transparent to the next layer of the OSI
model, the link layer. The link layer has two sublayers: the
Logical Link Control sublayer and the MAC sublayer. The
ICS1894-32 can interface directly with the MAC via MII/RMII
interface signals.
The ICS1894-32 transmits framed packets acquired from its
MAC Interface and receives encapsulated packets from
another PHY, which it translates and presents to its MAC
Interface.
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
5
ICS1894-32
REV M 021512
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