S29JL032J70TFI410 datasheet, PDF

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S29JL032J70TFI410: DescriptionAntennas GPS Act SMT Patch 10*10*4mm; Categorystorage storage; File Size699KB，61 Pages; ManufacturerCypress Semiconductor; Environmental Compliance

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S29JL032J70TFI410 Overview

Antennas GPS Act SMT Patch 10*10*4mm

S29JL032J70TFI410 Parametric

Parameter Name	Attribute value
Product Category	Flash Memory
Manufacturer	Cypress Semiconductor
RoHS	Details
Mounting Style	SMD/SMT
Package / Case	TSOP-48
Memory Size	32 Mbit
Interface Type	Parallel
Memory Type	NOR
Speed	70 ns
Supply Voltage - Max	3.6 V
Supply Voltage - Min	2.7 V
Supply Current - Max	16 mA
Operating Temperature Range	- 40 C to + 85 C
Packaging	Tray
Architecture	Sector
Data Bus Width	8 bit
Maximum Operating Temperature	+ 85 C
Minimum Operating Temperature	- 40 C
Organization	4 M x 8
Factory Pack Quantity	1
Timing Type	Asynchronous

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S29JL032J

32-Mbit (4M × 8-Bit/2M × 16-Bit), 3 V,

Simultaneous Read/Write Flash

Distinctive Characteristics

Architectural Advantages



Simultaneous Read/Write operations

– Data can be continuously read from one bank while executing

erase/program functions in another bank.

– Zero latency between read and write operations



Multiple bank architecture

– Four bank architectures available (refer to

Table 2 on page 12).



Boot sectors

– Top or bottom boot sector configurations available

– Any combination of sectors can be erased



Manufactured on 0.11 µm Process Technology



Secured Silicon Region:

Extra 256 byte sector

– Factory locked and identifiable: 16 bytes available for secure,

random factory Electronic Serial Number; verifiable as factory

locked through autoselect function

–

Customer lockable:

One-time programmable only. Once locked,

data cannot be changed



Zero power operation

– Sophisticated power management circuits reduce power

consumed during inactive periods to nearly zero.



Compatible with JEDEC standards

– Pinout and software compatible with single-power-supply flash

standard

– 2 mA active read current at 1 MHz

– 10 mA active read current at 5 MHz

– 200 nA in standby or automatic sleep mode



Cycling endurance: 100K cycles per sector



Data retention: 20 years typical

Software Features



Supports Common Flash Memory Interface (CFI)



Erase suspend/Erase resume

– Suspends erase operations to read data from, or program data to,

a sector that is not being erased, then resumes the erase

operation.



Data# polling and toggle bits

– Provides a software method of detecting the status of program or

erase operations



Unlock bypass program command

– Reduces overall programming time when issuing multiple

program command sequences

Hardware Features



Ready/Busy# output (RY/BY#)

– Hardware method for detecting program or erase cycle

completion



Hardware reset pin (RESET#)

– Hardware method of resetting the internal state machine to the

read mode



WP#/ACC input pin

– Write protect (WP#) function protects the two outermost boot

sectors regardless of sector protect status

– Acceleration (ACC) function accelerates program timing



Sector protection

– Hardware method to prevent any program or erase operation

within a sector

– Temporary Sector Unprotect allows changing data in protected

sectors in-system

Package Options



48-ball Fine-pitch BGA



48-pin TSOP

Performance Characteristics



High performance

– Access time as fast as 60 ns

– Program time: 6 µs/word typical using accelerated programming

function



Ultra low power consumption (typical values)

General Description

The S29JL032J is a 32 Mbit, 3.0 volt-only flash memory device, organized as 2,097,152 words of 16 bits each or 4,194,304 bytes

of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data appears on DQ7–DQ0. The device is designed to be

programmed in-system with the standard 3.0 volt V

supply, and can also be programmed in standard EPROM programmers.

The device is available with an access time of 60, or 70 ns and is offered in a 48-ball FBGA or a 48-pin TSOP package. Standard

control pins—chip enable (CE#), write enable (WE#), and output enable (OE#)—control normal read and write operations, and

avoid bus contention issues. The device requires only a single 3.0 volt power supply for both read and write functions. Internally

generated and regulated voltages are provided for the program and erase operations.

Cypress Semiconductor Corporation

Document Number: 002-00857 Rev. *H

•198 Champion Court•San Jose

CA 95134-1709•408-943-2600

Revised August 23, 2018

S29JL032J

Simultaneous Read/Write Operations with Zero Latency

The Simultaneous Read/Write architecture provides

simultaneous operation

by dividing the memory space into separate banks

(see

Table 2 on page 12).

Sector addresses are fixed, system software can be used to form user-defined bank groups.

During an Erase/Program operation, any of the non-busy banks may be read from.

Note that only two banks can operate

simultaneously.

The device can improve overall system performance by allowing a host system to program or erase in one bank,

then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the

completion of program or erase operations.

The S29JL032J can be organized with either a top or bottom boot sector configuration.

1.1

S29JL032J Features

The

Secured Silicon Region

is an extra 256 byte sector capable of being permanently locked by the customer. The Secured Silicon

Customer Indicator Bit (DQ6) is permanently set to 1 if the part has been locked and is 0 if lockable.

Customers may utilize the Secured Silicon Region as bonus space, reading and writing like any other flash sector, or may

permanently lock their own code there.

The device offers complete compatibility with the

JEDEC 42.4 single-power-supply Flash command set standard.

Commands

are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading

from other Flash or EPROM devices.

The host system can detect whether a program or erase operation is complete by using the device

status bits:

RY/BY# pin, DQ7

(Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to

the read mode.

The

sector erase architecture

allows memory sectors to be erased and reprogrammed without affecting the data contents of other

sectors. The device is fully erased when shipped from the factory.

Hardware data protection

measures include a low V

detector that automatically inhibits write operations during power

transitions. The

hardware sector protection

feature disables both program and erase operations in any combination of the sectors

of memory. This can be achieved in-system or via programming equipment.

The Erase Suspend/Erase Resume

feature enables the user to put erase on hold for any period of time to read data from, or

program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from

the Secured Silicon Region area (One Time Program area) after an erase suspend, then the user must use the proper command

sequence to enter and exit this region.

The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters

the

automatic sleep mode.

The system can also place the device into the

standby mode.

Power consumption is greatly reduced in

both modes.

Document Number: 002-00857 Rev. *H

Page 3 of 61

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