Tiny 16-/14-/12-Bit SPI
nanoDAC+,
with
±2 (16-Bit) LSB INL and 2 ppm/°C Reference
Data Sheet
FEATURES
Ultrasmall package: 2 mm × 2 mm, 8-lead LFCSP
High relative accuracy (INL): ±2 LSB maximum at 16 bits
AD5683R/AD5682R/AD5681R
Low drift, 2.5 V reference: 2 ppm/°C typical
Selectable span output: 2.5 V or 5 V
AD5683
External reference only
Selectable span output: V
REF
or 2 × V
REF
Total unadjusted error (TUE): 0.06% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.05% of FSR maximum
Low glitch: 0.1 nV-sec
High drive capability: 20 mA
Low power: 1.2 mW at 3.3 V
Independent logic supply: 1.62 V logic compatible
Wide operating temperature range: −40°C to +105°C
Robust 4 kV HBM ESD protection
AD5683R/AD5682R/AD5681R/AD5683
FUNCTIONAL BLOCK DIAGRAM
V
LOGIC
*
V
REF
V
DD
POWER-ON
RESET
2.5V
REF
REF
16-/14-/12-BIT
DAC
OUTPUT
BUFFER
V
OUT
LDAC
AD5683R/
AD5682R/
AD5681R
DAC
REGISTER
RESET
INPUT
CONTROL LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
*NOT AVAILABLE IN ALL THE MODELS
SYNC SCLK SDI SDO*
GND
11955-001
Figure 1.
AD5683R/AD5682R/AD5681R
MSOP
(For more information, see the Functional Block Diagrams—LFCSP section.)
APPLICATIONS
Process controls
Data acquisition systems
Digital gain and offset adjustment
Programmable voltage sources
GENERAL DESCRIPTION
The
AD5683R/AD5682R/AD5681R/AD5683,
members of the
nanoDAC+®
family, are low power, single-channel, 16-/14-/12-bit
buffered voltage out digital-to-analog converters (DACs). The
devices, except the
AD5683,
include an enabled by default internal
2.5 V reference, offering 2 ppm/°C drift. The output span can be
programmed to be 0 V to V
REF
or 0 V to 2 × V
REF
. All devices
operate from a single 2.7 V to 5.5 V supply and are guaranteed
monotonic by design. The devices are available in a 2.00 mm ×
2.00 mm, 8-lead LFCSP or a 10-lead MSOP.
The internal power-on reset circuit ensures that the DAC register
is written to zero scale at power-up while the internal output
buffer is configured in normal mode. The
AD5683R/AD5682R
/AD5681R/AD5683 contain a power-down mode that reduces
the current consumption of the device to 2 µA (maximum) at 5 V
and provides software selectable output loads while in power-
down mode.
The
AD5683R/AD5682R/AD5681R/AD5683
use a versatile
3-wire serial interface that operates at clock rates of up to 50 MHz.
Some devices also include asynchronous RESET pin and V
LOGIC
pin options, allowing 1.8 V compatibility.
Rev. D
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Table 1. Single-Channel
nanoDAC+
Portfolio
Interface
SPI
I
2
C
Reference
Internal
External
Internal
External
16-Bit
AD5683R
AD5683
AD5693R
AD5693
14-Bit
AD5682R
AD5692R
12-Bit
AD5681R
AD5691R
PRODUCT HIGHLIGHTS
1.
2.
High Relative Accuracy (INL).
AD5683R/AD5683
(16-bit): ±2 LSB maximum.
Low Drift, 2.5 V On-Chip Reference.
2 ppm/°C typical temperature coefficient.
5 ppm/°C maximum temperature coefficient.
Two Package Options.
2.00 mm × 2.00 mm, 8-lead LFCSP.
10-lead MSOP.
3.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD5683R/AD5682R/AD5681R/AD5683
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagrams—LFCSP............................................. 3
Specifications..................................................................................... 4
AC Characteristics ........................................................................ 6
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings ............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution .................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 17
Theory of Operation ...................................................................... 19
Data Sheet
Digital-to-Analog Converter .................................................... 19
Transfer Function ....................................................................... 19
DAC Architecture....................................................................... 19
Serial Interface ................................................................................ 21
SPI Serial Data Interface ............................................................ 21
Short Write Operation (AD5681R Only) ................................ 21
Internal Registers........................................................................ 23
Commands .................................................................................. 23
Hardware LDAC ......................................................................... 25
Hardware RESET ........................................................................ 25
Thermal Hysteresis .................................................................... 26
Power-Up Sequence ................................................................... 26
Recommended Regulator .......................................................... 26
Layout Guidelines....................................................................... 26
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 28
REVISION HISTORY
12/2016—Rev. C to Rev. D
Changed 1.8 V to 1.62 V, 1.8 V – 10% to 1.62 V, 5 V + 10% to 5.5 V,
and 1.8 V ≤ V
LOGIC
≤ 2.7 V to 1.62 V ≤ V
LOGIC
≤ 2.7 V.....Throughout
Changes to DC Power Supply Rejection Ratio, PSRR, Test
Conditions/Comments Column, Table 2......................................... 4
3/2016—Rev. B to Rev. C
Changes to Features Section............................................................ 1
Changes to Specifications Section .................................................. 4
Changes to Table 2 ............................................................................ 5
Changes to AC Characteristics Section, Timing Characteristics
Section, and Table 4 .......................................................................... 6
Changes to Figure 4 .......................................................................... 7
Changes to Table 7 ............................................................................ 9
Changes to Table 8 .......................................................................... 10
Changes to Terminology Section.................................................. 17
Changes to SPI Serial Data Interface Section ............................. 21
10/2014—Rev. A to Rev. B
Changes to Table 1.............................................................................1
Changes to Figure 14...................................................................... 11
Added Recommended Regulator Section ................................... 26
Changes to Ordering Guide .......................................................... 28
1/2014—Rev. 0 to Rev. A
Change to Features Section ..............................................................1
Removed Endnote 2, Endnote 3, Endnote 5, and Endnote 6,
Table 2; Renumbered Sequentially ..................................................5
Removed Endnote 2, Table 3; Renumbered Sequentially ............6
Removed Endnote 1, Table 4; Renumbered Sequentially ............6
Changes to Table 5.............................................................................8
Removed Solder Heat Reflow Section and Figure 53;
Renumbered Sequentially ............................................................. 25
12/2013—Revision 0: Initial Version
Rev. D | Page 2 of 28
Data Sheet
FUNCTIONAL BLOCK DIAGRAMS—LFCSP
V
LOGIC
*
V
REF
V
DD
LDAC*
POWER-ON
RESET
2.5V
REF
REF
16-/14-/12-BIT
DAC
AD5683R/AD5682R/AD5681R/AD5683
AD5683R/
AD5682R/
AD5681R
OUTPUT
BUFFER
V
OUT
DAC
REGISTER
RESET*
INPUT
CONTROL LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
*NOT AVAILABLE IN ALL THE MODELS
SYNC SCLK SDI
GND
11955-002
Figure 2.
AD5683R/AD5682R/AD5681R
LFCSP
V
REF
V
DD
POWER-ON
RESET
AD5683
LDAC*
DAC
REGISTER
REF
16-BIT
DAC
OUTPUT
BUFFER
V
OUT
INPUT
CONTROL LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
SYNC SCLK SDI
GND
Figure 3.
AD5683
LFCSP
Rev. D | Page 3 of 28
11955-003
AD5683R/AD5682R/AD5681R/AD5683
SPECIFICATIONS
Data Sheet
V
DD
= 2.7 V to 5.5 V, R
L
= 2 kΩ to GND, C
L
= 200 pF to GND, V
REF
= 2.5 V, V
LOGIC
= 1.62 V to 5.5 V, −40°C < T
A
< +105°C, unless otherwise
noted.
Table 2.
Parameter
STATIC PERFORMANCE
1
AD5683R
Resolution
Relative Accuracy, INL
A Grade
B Grade
Differential Nonlinearity, DNL
AD5683
Resolution
Relative Accuracy, INL
Differential Nonlinearity, DNL
AD5682R
Resolution
Relative Accuracy, INL
Differential Nonlinearity, DNL
AD5681R
Resolution
Relative Accuracy, INL
Differential Nonlinearity, DNL
Zero-Code Error
Offset Error
Full-Scale Error
Gain Error
Total Unadjusted Error, TUE
Min
Typ
Max
Unit
Test Conditions/Comments
16
±8
±2
±3
±1
16
±2
±3
±1
14
±1
±1
12
±1
±1
1.25
±1.5
±0.075
±0.05
±0.16
±0.14
±0.075
±0.06
±1
±1
±1
0.2
0
0
2
10
1
10
10
30
20
V
REF
2 × V
REF
Bits
LSB
LSB
LSB
LSB
Bits
LSB
LSB
LSB
Bits
LSB
LSB
Bits
LSB
LSB
mV
mV
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
µV/°C
µV/°C
ppm/°C
mV/V
V
V
nF
nF
kΩ
µV/mA
µV/mA
mA
Ω
Gain = 2
Gain = 1
Guaranteed monotonic by design
Gain = 2
Gain =1
Guaranteed monotonic by design
Guaranteed monotonic by design
Guaranteed monotonic by design
All 0s loaded to DAC register
All 1s loaded to DAC register
Internal reference, gain = 1
Internal reference, gain = 2
External reference, gain = 1
External reference, gain = 2
Zero-Code Error Drift
Offset Error Drift
Gain Temperature Coefficient
DC Power Supply Rejection Ratio, PSRR
OUTPUT CHARACTERISTICS
Output Voltage Range
Capacitive Load Stability
Resistive Load
Load Regulation
Short-Circuit Current
Load Impedance at Rails
2
DAC code = midscale; V
DD
= 5 V
Gain = 1
Gain = 2
R
L
= ∞
R
L
= 2 kΩ
C
L
= 0 µF
5 V, DAC code = midscale; −30 mA ≤ I
OUT
≤ +30 mA
3 V, DAC code = midscale; −20 mA ≤ I
OUT
≤ +20 mA
20
50
Rev. D | Page 4 of 28
Data Sheet
Parameter
REFERENCE OUTPUT
Output Voltage
Voltage Reference TC
3
A-Grade
B-Grade
Output Impedance
Output Voltage Noise
Output Voltage Noise Density
Capacitive Load Stability
Load Regulation Sourcing
Load Regulation Sinking
Output Current Load Capability
Line Regulation
Thermal Hysteresis
REFERENCE INPUT
Reference Current
Reference Input Range
Reference Input Impedance
LOGIC INPUTS
I
IN
, Input Current
V
INL
, Input Low Voltage
4
V
INH
, Input High Voltage
4
C
IN
, Pin Capacitance
LOGIC OUTPUTS (SDO)
5
Output Low Voltage, V
OL
Output High Voltage, V
OH
Pin Capacitance
POWER REQUIREMENTS
V
LOGIC5
I
LOGIC5
V
DD
I
DD6
Normal Mode
7
Power-Down Modes
8
1
AD5683R/AD5682R/AD5681R/AD5683
Min
2.4975
5
2
0.05
16.5
250
5
50
30
±5
80
125
25
26
47
1
120
60
±1
0.3 × V
DD
0.7 × V
DD
2
0.4
V
DD
− 0.4
4
1.62
0.25
2.7
V
REF
+ 1.5
350
110
5.5
3
5.5
5.5
500
180
2
V
DD
Typ
Max
2.5025
20
5
Unit
V
ppm/°C
ppm/°C
Ω
µV p-p
nV/√Hz
µF
µV/mA
µV/mA
mA
µV/V
ppm
ppm
µA
µA
V
kΩ
kΩ
µA
V
V
pF
V
V
pF
V
µA
V
V
µA
µA
µA
Test Conditions/Comments
At ambient
See the Terminology section
0.1 Hz to 10 Hz
At ambient; f = 10 kHz, C
L
= 10 nF
R
L
= 2 kΩ
At ambient; V
DD
≥ 3 V
At ambient
V
DD
≥ 3 V
At ambient
First cycle
Additional cycles
V
REF
= V
DD
= V
LOGIC
= 5 V, gain = 1
V
REF
= V
DD
= V
LOGIC
= 5 V, gain = 2
Gain = 1
Gain = 2
Per pin
I
SINK
= 200 μA
I
SOURCE
= 200 μA
V
IH
= V
LOGIC
or V
IL
= GND
Gain = 1
Gain = 2
V
IH
= V
DD
, V
IL
= GND
Internal reference enabled
Internal reference disabled
Linearity is calculated using a reduced code range:
AD5683R
and
AD5683
(Code 512 to Code 65,535);
AD5682R
(Code 128 to Code 16,384);
AD5681R
(Code 32 to
Code 4096). Output unloaded.
2
When drawing a load current at either rail, the output voltage headroom, with respect to that rail, is limited by the 20 Ω typical channel resistance of the output
devices; for example, when sinking 1 mA, the minimum output voltage = 20 Ω, 1 mA generates 20 mV. See Figure 38 (Headroom/Footroom vs. Load Current).
3
Reference temperature coefficient is calculated as per the box method. See the Terminology section for more information.
4
Substitute V
LOGIC
for V
DD
if device includes a V
LOGIC
pin.
5
The V
LOGIC
and SDO pins are not available on all models.
6
If the V
LOGIC
pin is not available, I
DD
= I
DD
+ I
LOGIC
.
7
Interface inactive. DAC active. DAC output unloaded.
8
DAC powered down.
Rev. D | Page 5 of 28
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