Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Recommended DC Operating Conditions
(T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
Supply Voltage
ST
and
PBRST
Input High Level
(Note 1)
ST
and
PBRST
Input Low Level
SYMBOL
V
CC
V
IH
V
IL
CONDITIONS
MIN
4.5
2.0
-0.3
TYP
5.0
MAX
5.5
V
CC
+ 0.3
+0.8
UNITS
V
V
V
DC Electrical Characteristics
(V
CC
= +4.5V to +5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
Input Leakage
ST,
TOL
Output Current RST
Output Current RST,
RST
Operating Current (Note 2)
V
CC
5% Trip Point (Note 3)
V
CC
10% Trip Point (Note 3)
SYMBOL
I
IL
I
OH
I
OL
I
CC
V
CCTP
V
CCTP
TOL = GND
TOL = V
CC
4.50
4.25
V
OH
= 2.4V
V
OL
= 0.4V
CONDITIONS
MIN
-1.0
-1.0
2.0
-12
10
50
4.62
4.37
200
4.74
4.49
TYP
MAX
+1.0
UNITS
µA
mA
mA
µA
V
V
Capacitance (Note 4)
(T
A
= +25°C, unless otherwise noted.)
PARAMETER
Input Capacitance
ST,
TOL
Output Capacitance RST,
RST
SYMBOL
C
IN
C
OUT
CONDITIONS
MIN
TYP
MAX
5
7
UNITS
pF
pF
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Maxim Integrated │
2
MAX1232
Microprocessor Monitor
AC Electrical Characteristics
(V
CC
= +5V ±10%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
PBRST
(Note 5)
PBRST
Delay
Reset Active Time
ST
Pulse Width
ST
Timeout Period
V
CC
Fall Time (Note 4)
V
CC
Rise Time (Note 4)
V
CC
Detect to RST High and
RST
Low
V
CC
Detect to RST Low and
RST
Open (Note 6)
Note
Note
Note
Note
Note
Note
1:
2:
3:
4:
5:
6:
SYMBOL
t
PB
t
PBD
t
RST
t
ST
t
TD
t
F
t
B
t
BPD
t
BPU
Figure 4
Figure 4, TD pin = 0V
TD pin = open
TD pin = V
CC
Figure 5
Figure 6
Figure 7, V
CC
falling
Figure 8, V
CC
rising
250
610
Figure 3
Figure 3
CONDITIONS
MIN
20
1
250
75
62.5
250
500
10
0
100
1000
150
600
1200
250
1000
2000
µs
µs
ns
ms
ms
4
610
20
1000
TYP
MAX
UNITS
ms
ms
ms
ns
PBRST
is internally pulled up to V
CC
with an internal impedance of typically 40kΩ.
Measured with outputs open.
All voltages referenced to GND.
Guaranteed by design.
PBRST
must be held low for a minimum of 20ms to guarantee a reset.
t
R
= 5μs.
Pin Description
PIN
WIDE SO
1, 3, 5, 7, 10,
12, 14, 16
2
4
6
8
DIP/SO
—
1
2
3
4
NAME
N.C.
PBRST
TD
TOL
GND
No Connection
Pushbutton Reset Input. A debounced active-low input that ignores pulses less than 1ms
in duration and is guaranteed to recognize inputs of 20ms or greater.
Time Delay Set. The watchdog timebase select input (t
TD
= 150ms for TD = 0V,
t
TD
= 600ms for TD = open, t
TD
= 1.2s for TD = V
CC
).
Tolerance Input. Connect to GND for 5% tolerance or to V
CC
for 10% tolerance.
Ground
Reset Output (Active High). Goes active:
(1) If V
CC
falls below the selected reset voltage threshold.
(2) If
PBRST
is forced low.
(3) If
ST
is not strobed within the minimum timeout period.
(4) During power-up.
Reset Output (Active Low, Open Drain). See RST.
Strobe Input. Input for watchdog timer.
+5V Power-Supply Input
FUNCTION
9
5
RST
11
13
15
6
7
8
RST
ST
V
CC
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Maxim Integrated │
3
MAX1232
Microprocessor Monitor
Detailed Description
Power Monitor
A voltage detector monitors V
CC
and holds the reset
outputs (RST and
RST)
in their active states whenever
V
CC
is below the selected 5% or 10% tolerance (4.62V
or 4.37V, typically). To select the 5% level, connect TOL
to ground. To select the 10% level, connect TOL to V
CC
.
The reset outputs will remain in their active states until
V
CC
has been continuously in-tolerance for a minimum of
250ms (the reset active time) to allow the power supply
and μP to stabilize.
The RST output both sinks and sources current, while the
RST
output, an open-drain MOSFET, sinks current only
and must be pulled high.
Watchdog Timer
The microprocessor drives the
ST
input with an input/
output (I/O) line. The microprocessor must toggle the
ST
input within a set period (as determined by TD) to verify
proper software execution. If a hardware or software fail-
ure keeps
ST
from toggling within the minimum timeout
period—ST is activated only by falling edges (a high-to-
low transition)—the MAX1232 reset outputs are forced to
their active states for 250ms (Figure 2). This typically initi-
ates the microprocessor’s power-up routine. If the inter-
ruption continues, new reset pulses are generated each
timeout period until
ST
is strobed. The timeout period is
determined by the TD input connection. This timeout peri-
od is typically 150ms with TD connected to GND, 600ms
with TD floating, or 1200ms with TD connected to V
CC
.
The software routine that strobes
ST
is critical. The code
must be in a section of software that executes frequently
enough so the time between toggles is less than the
watchdog timeout period. One common technique con-
trols the microprocessor I/O line from two sections of the
program. The software might set the I/O line high while
operating in the foreground mode, and set it low while in
the background or interrupt mode. If both modes do not
execute correctly, the watchdog timer issues reset pulses.
Pushbutton Reset Input
The MAX1232’s debounced manual reset input (PBRST)
manually forces the reset outputs into their active states.
The reset outputs go active after
PBRST
has been held
low for a time t
PBD
, the pushbutton reset delay time. The
reset outputs remain in their active states for a minimum
of 250ms after
PBRST
rises above V
IH
(Figure 3).
A mechanical pushbutton or an active logic signal can
drive the
PBRST
input. The debounced input ignores
input pulses less than 1ms and is guaranteed to recog-
nize pulses of 20ms or greater. The
PBRST
input has
an internal pullup to V
CC
of about 100μA; therefore, an
external pullup resistor is not necessary.
+5V
+5V
10kΩ
V
CC
PB RST
TD
ST
RST
I/O
MICROPROCESSOR
RESET
+8V
7805
+5V
3-TERMINAL
REGULATOR
V
CC
0.10µF
RST
RESET
MICROPROCESSOR
ST
TD
TOL
GND
I/O
MAX1232
MAX1232
GND
TOL
Figure 1. Pushbutton Reset
Figure 2. Watchdog Timer
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Maxim Integrated │ 4
MAX1232
Microprocessor Monitor
t
ST
ST
t
PB
PB RST
t
PBD
V
IH
V
IL
t
RST
t
TD
NOTE:
t
SD
IS THE MAXIMUM ELAPSED TIME BETWEEN ST HIGH-TO-LOW
TRANSITIONS (ST IS ACTIVATED BY FALLING EDGES ONLY) WHICH WILL
KEEP THE WATCHDOG TIMER FROM FORCING THE RESET OUTPUTS
ACTIVE FOR A TIME OF t
RST
. t
TD
IS A FUNCTION OF THE VOLTAGE AT
THE TD PIN, AS TABULATED BELOW.
CONDITION
TD pin = 0V
TD pin = open
TD pin = V
CC
MIN
62.5ms
250ms
500ms
t
TD
TYP
150ms
250ms
1200ms
MAX
250ms
1000ms
2000ms
RST
RST
Figure 3. Pushbutton Reset. The debounced PBRST input
ignores input pulses less than 1ms and is guaranteed to
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