Data Sheet
FEATURES
Pair of VGAs with rms AGC detectors
VGA and AGC modes of operation
Continuous gain control range: 48 dB
Noise figure (NF) = 6.8 dB at maximum gain
IMD3 > 62 dBc for 1.0 V p-p composite output
Differential input and output
Multiplexed inputs for VGA2
Programmable detector AGC setpoints
Programmable VGA maximum gain
Power-down feature
Single 5 V supply operation
Cascadable IF VGAs with
Programmable RMS Detectors
ADL5336
FUNCTIONAL BLOCK DIAGRAM
COM
OPP1 OPM1 IP2A IM2A COM IP2B IM2B
VCM1
VPOS
VGA1
INP1
INM1
VPOS
COM
MODE
SPI
VGA2
VCM2
VPOS
OPP2
OPM2
X
2
X
2
VPOS
ADL5336
COM
SDO
DATA
09550-001
APPLICATIONS
Point-to-multipoint radios
Instrumentation
Medical
ENBL
GAIN1 DTO1 GAIN2 DTO2 COMD VPSD
LE
CLK
Figure 1.
GENERAL DESCRIPTION
The
ADL5336
consists of a pair of variable gain amplifiers
(VGAs) designed for cascaded IF applications. The amplifiers
have linear-in-dB gain control and operate from low frequencies to
1 GHz. Their excellent gain conformance over the control range
and flatness over frequency are due to Analog Devices, Inc.,
patented X-AMP® architecture, an innovative technique for
implementing high performance variable gain control.
Each VGA has 24 dB of gain control range. Their maximum gain
can be independently programmable over a 6 dB range via the
SPI. The VGAs can be cascaded to provide a total range of 48 dB.
When connected to a 50 Ω source through a 1:4 balun, the gain
is 6 dB higher. The second VGA has an SPI programmable input
switch that selects one of two external inputs.
When driven from a 200 Ω source or from a 50 Ω source through
a 1:4 balun, the noise figure (NF) for the composite amplifier is
6.8 dB at maximum gain. The output of each VGA can drive
100 Ω loads to 5 V p-p maximum.
Each VGA has an independent square law detector for autonomous,
automatic gain control (AGC) operation. Each detector setpoint
can be programmed independently through the SPI from −24 dBV
to −3 dBV in 3 dB steps. When both VGAs are arranged in AGC
mode and are programmed to the same setpoint, the composite NF
increases to 9 dB when backed off by 18 dB from maximum gain.
The
ADL5336
operates from a 5 V supply and consumes a typical
supply current of 80 mA. When disabled, it consumes 4 mA. It is
fabricated in an advanced silicon-germanium BiCMOS process and
is available in a 32-lead exposed paddle LFCSP package. Performance
is specified over a −40°C to +85°C temperature range.
Rev. B
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ADL5336* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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REFERENCE MATERIALS
Product Selection Guide
•
RF Source Booklet
EVALUATION KITS
•
ADL5336 Evaluation Board
DESIGN RESOURCES
•
ADL5336 Material Declaration
•
PCN-PDN Information
•
Quality And Reliability
•
Symbols and Footprints
DOCUMENTATION
Data Sheet
•
ADL5336: Cascadable IF VGAs with Programmable RMS
Detectors Data Sheet
SOFTWARE AND SYSTEMS REQUIREMENTS
•
ADL5336 Evaluation Board Software
•
Windows 7 Drivers for the SPI Software
DISCUSSIONS
View all ADL5336 EngineerZone Discussions.
SAMPLE AND BUY
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TOOLS AND SIMULATIONS
• ADIsimPLL™
•
ADIsimRF
TECHNICAL SUPPORT
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number.
REFERENCE DESIGNS
•
CN0248
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ADL5336
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Diagrams.......................................................................... 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 17
Circuit Description..................................................................... 17
Gain Control Interface ............................................................... 18
Input and Output Impedances.................................................. 18
AGC Operation........................................................................... 18
Register Map and Codes ................................................................ 19
Applications Information .............................................................. 20
Basic Connections ...................................................................... 20
Data Sheet
Supply Decoupling ..................................................................... 20
Input Signal Path ........................................................................ 20
Output Signal Path ..................................................................... 20
Detector Output and Gain Pin ................................................. 21
Common-Mode Bypassing ....................................................... 21
Serial Port Connections............................................................. 21
Mode and Enable Connections ................................................ 21
Error Vector Magnitude (EVM) ............................................... 21
Effect of C
AGC
on EVM............................................................... 22
AGC Insensitivity to Modulation Type ................................... 22
Effect of Setpoint on EVM ........................................................ 23
Cascaded VGA/AGC Performance.......................................... 23
Evaluation Board Layout ............................................................... 25
Bill of Materials (BOM) ............................................................. 28
Evaluation Board Control Software ......................................... 29
Outline Dimensions ....................................................................... 30
Ordering Guide .......................................................................... 30
REVISION HISTORY
2/12—Rev. A to Rev. B
Changes to Figure 70 ...................................................................... 25
Changes to Figure 71 and Figure 72............................................. 26
Changes to Table 11 ........................................................................ 28
Changes to Figure 73 ...................................................................... 29
Updated Outline Dimensions ....................................................... 30
6/11—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................ 3
Changes to Typical Performance Charteristics
Section Format .................................................................................. 8
Changes to Figure 7 and Figure 10................................................. 8
Changes to Figure 11 to Figure 16.................................................. 9
Changes to Figure 17 to Figure 22................................................ 10
Changes to Figure 23 and Figure 26............................................. 11
Inserted Figure 53 and Figure 56; Renumbered Sequentially .. 16
Changes to Figure 60 ...................................................................... 17
Changes to Figure 61 Caption....................................................... 18
Changes to Cascaded VGA/AGC Performance Section and
Figure 68 .......................................................................................... 24
Changes to Figure 72 ...................................................................... 26
2/11—Revision 0: Initial Version
Rev. B | Page 2 of 32
Data Sheet
SPECIFICATIONS
ADL5336
V
S
= 5 V, T
A
= 25°C, Z
S
= 200 Ω, Z
L VGA1
= 200 Ω, Z
L VGA2
= 100 Ω, RF input = −20 dBm at 140 MHz, maximum gain setting for both VGAs,
unless otherwise noted. 1:4 balun voltage gain is not included. All dBm numbers are with respect to each VGA’s load impedance.
Table 1.
Parameter
OVERALL FUNCTION
Frequency Range
Maximum Input
Maximum Output
AC Input Impedance
VGA1
VGA2 Selected Input
VGA2 Unselected Input
AC Output Impedance
GAIN CONTROL INTERFACE
Voltage Gain Range
VGA1
Test Conditions/Comments
3 dB bandwidth
INP1/INM1, IP2A/IM2A, IP2B/IM2B differential
OPP1/OPM1, OPP2/OPM2 differential at P1dB
Differential across INP1, INM1
Differential across IP2A, IM2A or IP2B, IM2B
VGA1
VGA2
GAIN1/GAIN2, MODE
GAIN1/GAIN2 from 0 V to 1 V
Gain Code 00
Gain Code 01
Gain Code 10
Gain Code 11
Gain Code 00
Gain Code 01
Gain Code 10
Gain Code 11
8.5 dB Gain Step
MODE = V
S
V
GAINx
from 0.2 V to 0.8 V
V
GAINx
to COM
VGA1, Gain Code 00, V
GAIN
= 1 V
VGA2, Gain Code 11, V
GAIN
= 1 V
VGA1, Gain Code 00, V
GAIN
= 1 V
VGA1, Gain Code 11, V
GAIN
= 1 V
VGA2, Gain Code 00, V
GAIN
= 1 V
VGA2, Gain Code 11, V
GAIN
= 1 V
VGA1, Gain Code 00, V
GAIN
= 1 V
VGA1, Gain Code 11, V
GAIN
= 1 V
VGA2, Gain Code 00, V
GAIN
= 1 V
VGA2, Gain Code 11, V
GAIN
= 1 V
Min
LF
8
5
200
200
10
1
3.5
Typ
Max
1000
Unit
MHz
V p-p
V p-p
Ω
Ω
kΩ
Ω
Ω
VGA2
−14.6
−12.2
−10.3
−8.9
−10.8
−8.2
−6.6
−4.7
5
35
35
±0.2
4.6
7.4
7.1
21 (28)
18 (25)
26 (36)
24 (34)
3.5(10.5)
3.5(10.5)
4 (14)
4 (14)
+9.7
+12
+13.8
+15.2
+13.4
+15.9
+17.7
+19.5
dB
dB
dB
dB
dB
dB
dB
dB
ns
mV/dB
mV/dB
dB
MΩ
dB
dB
dBV (dBm)
dBV (dBm)
dBV (dBm)
dBV (dBm)
dBV (dBm)
dBV (dBm)
dBV (dBm)
dBV (dBm)
Gain Step Response Time
Gain Slope
VGA1
VGA2
Gain Error
Input Impedance
f = 140 MHz
Noise Figure
Output IP3
Output Voltage Level of 1.0 V p-p
Output P1dB
Rev. B | Page 3 of 32
ADL5336
Parameter
f = 350 MHz
Noise Figure
Output IP3
Output Voltage Level of 1.0 V p-p
Test Conditions/Comments
VGA1, Gain Code 00, V
GAIN
= 1 V
VGA2, Gain Code 11, V
GAIN
= 1 V
VGA1, Gain Code 00, V
GAIN
= 1 V
VGA1, Gain Code 11, V
GAIN
= 1 V
VGA2, Gain Code 00, V
GAIN
= 1 V
VGA2, Gain Code 11, V
GAIN
= 1 V
VGA1, Gain Code 00, V
GAIN
= 1 V
VGA1, Gain Code 11, V
GAIN
= 1 V
VGA2, Gain Code 00, V
GAIN
= 1 V
VGA2, Gain Code 11, V
GAIN
= 1 V
DTO1, DTO2
SPI controlled, 3 dB steps
5 dB input step, C
AGC
= 0.1 µF
LE, CLK, DATA, SDO
Min
Typ
8
7.7
12 (19)
10.5(17.5)
18 (28)
16 (26)
0 (7)
0 (7)
−1.5 (+8.5)
−1.5 (+8.5)
−24
0.1
1.5
>2.2
<1.8
<1
2
LE, CLK, DATA, SDO
DATA hold time
DATA setup time
LE hold time
LE setup time
CLK high pulse width
CLK-to-SDO delay
VPOS, VPSD, COM, COMD, ENBL
4.5
ENBL = 5 V
ENBL = 0 V
Delay following low-to-high transition until
device meets full specifications in VGA mode
Delay following high-to-low transition until
device produces full attenuation in VGA mode
20
5
5
5
5
5
5
5
80
4
2.3
800
20
5.5
Data Sheet
Max
Unit
dB
dB
dBV (dBm)
dBV (dBm)
dBV (dBm)
dBV (dBm)
dBV (dBm)
dBV (dBm)
dBV (dBm)
dBV (dBm)
−3
V
S
/2
dBV
V
ms
V
V
µA
pF
MHz
ns
ns
ns
ns
ns
ns
V
mA
mA
V
ns
ns
Output P1dB
SQUARE LAW DETECTORS
Output Setpoint
Output Range
AGC Step Response Range
DIGITAL LOGIC
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
INH
/I
INL
Input Capacitance, C
IN
SPI TIMING
f
CLK
t
DH
t
DS
t
LH
t
LS
t
PW
t
D
POWER AND ENABLE
Supply Voltage Range
Total Supply Current
Disable Current
Disable Threshold
Enable Response Time
Disable Response Time
Rev. B | Page 4 of 32
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