Features
•
Industry-standard Architecture
– Emulates Many 24-pin PALs
®
– Low-cost Easy-to-use Software Tools
•
High-speed Electrically-erasable Programmable Logic Devices
– 7.5 ns Maximum Pin-to-pin Delay
•
Several Power Saving Options
Device
ATF20V8B
ATF20V8BQ
ATF20V8BQL
I
CC
, Standby
50 mA
35 mA
5 mA
I
CC
, Active
55 mA
40 mA
20 mA
•
CMOS and TTL Compatible Inputs and Outputs
•
Input and I/O Pull-up Resistors
•
Advanced Flash Technology
•
– Reprogrammable
– 100% Tested
High-reliability CMOS Process
– 20 Year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latchup Immunity
Commercial and Industrial Temperature Ranges
Dual-in-line and Surface Mount Packages in Standard Pinouts
PCI-Compliant
Green Package Options (Pb/Halide-free/RoHS Complant) Available
High-
performance
EE PLD
ATF20V8B
ATF20V8BQ
ATF20V8BQL
•
•
•
•
Block Diagram
Pin Configurations
All Pinouts Top View
Pin Name
CLK
I
I/O
OE
*
VCC
Function
Clock
Logic Inputs
Bi-directional Buffers
Output Enable
No Internal Connection
+5V Supply
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
TSSOP
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
IN
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
OE/IN
DIP/SOIC
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
IN
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
OE/IN
PLCC
IN
IN
CLK/IN
*
VCC
IN
I/O
4
3
2
1
28
27
26
IN
IN
IN
*
IN
IN
IN
5
6
7
8
9
10
11
25
24
23
22
21
20
19
I/O
I/O
I/O
*
I/O
I/O
I/O
IN
IN
GND
*
OE/IN
IN
I/O
12
13
14
15
16
17
18
Rev. 0407J–07/06
1
Description
The ATF20V8B is a high-performance CMOS (electrically-
erasable) programmable logic device (PLD) that utilizes
Atmel’s proven electrically-erasable Flash memory technol-
ogy. Speeds down to 7.5 ns and power dissipation as low
as 10 mA are offered. All speed ranges are specified over
the full 5V
±
10% range for industrial temperature ranges,
and 5V
±
5% for commercial temperature ranges.
Several low-power options allow selection of the best solu-
tion for various types of power-limited applications. Each of
these options significantly reduces total system power and
enhances system reliability.
The ATF20V8Bs incorporate a superset of the generic
architectures, which allows direct replacement of the 20R8
family and most 24-pin combinatorial PLDs. Eight outputs
are each allocated eight product terms. Three different
modes of operation, configured automatically with soft-
ware, allow highly complex logic functions to be realized.
Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V
(1)
Note:
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V
(1)
1.
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Minimum voltage is -0.6V DC which may under-
shoot to -2.0V for pulses of less than 20 ns.Maxi-
mum output pin voltage is V
CC
+ 0.75V DC which
may overshoot to 7.0V for pulses of less than 20
ns.
DC and AC Operating Conditions
Commercial
Operating Temperature (Ambient)
V
CC
Power Supply
0°C - 70°C
5V
±
5%
Industrial
-40°C - 85°C
5V
±
10%
2
ATF20V8B(Q)(L)
ATF20V8B(Q)(L)
DC Characteristics
Symbol
I
IL
I
IH
Parameter
Input or I/O Low
Leakage Current
Input or I/O High
Leakage Current
Condition
0
≤
V
IN
≤
V
IL
(Max)
3.5
≤
V
IN
≤
V
CC
Com.
B-7, -10
Ind.
B-15
B-15
Power Supply
Current, Standby
V
CC
= Max,
V
IN
= Max,
Outputs Open
B-25
B-25
BQ-10
BQL-15
BQL-15
BQL-25
BQL-25
B-7, -10
Ind.
B-15
B-15
Clocked Power
Supply Current
V
CC
= Max,
Outputs Open,
f = 15 MHz
B-25
B-25
BQ-10
BQL-15
BQL-15
BQL-25
BQL-25
IOS
(1)
V
IL
V
IH
V
OL
Output Short
Circuit Current
Input Low Voltage
Input High Voltage
V
IN
= V
IH
or V
IL
,
V
CC
= Min
V
IN
= V
IH
or V
IL
,
V
CC
= Min
I
OL
= 24 mA
I
OL
= 16 mA
I
OH
= -4.0 mA
2.4
Com.,
Ind.
V
OUT
= 0.5V
-0.5
2.0
Com.
Ind.
Com.
Ind.
Com.
Com.
Ind.
Com.
Ind.
80
60
60
60
60
40
20
20
20
20
125
90
105
90
105
55
35
40
35
40
-130
0.8
V
CC
+ 0.75
0.5
0.5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
V
Com.
Ind.
Com.
Ind.
Com.
Com.
Ind.
Com.
Ind.
Com.
60
60
60
60
60
35
5
5
5
5
80
100
80
90
80
90
55
10
15
10
15
110
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
60
Min
Typ
-35
Max
-100
10
90
Units
µA
µA
mA
I
CC
I
CC2
Output Low Voltage
V
OH
Notes:
Output High Voltage
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
2. Shaded parts are obsolete with a last time buy date of 19 August 1999.
3
AC Waveforms
(1)
Note:
1.
Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics
(1)
-7
Symbol
t
PD
t
CF
t
CO
t
S
t
H
t
P
t
W
Parameter
Input or Feedback to
Non-Registered Output
Clock to Feedback
Clock to Output
Input or Feedback
Setup Time
Hold Time
Clock Period
Clock Width
External Feedback 1/(t
S
+ t
CO
)
f
MAX
Internal Feedback 1/(t
S
+ t
CF
)
No Feedback 1/(t
P
)
t
EA
t
ER
t
PZX
t
PXZ
Note:
1.
2.
3.
Input to Output Enable — Product Term
Input to Output Disable —Product Term
OE pin to Output Enable
OE pin to Output Disable
3
2
2
1.5
2
5
0
8
4
100
125
125
9
9
6
6
3
2
2
1.5
8 outputs switching
1 output switching
Min
3
Max
7.5
7
3
5
2
7.5
0
12
6
68
74
83
10
10
10
10
3
2
2
1.5
6
7
2
12
0
16
8
45
50
62
15
15
15
15
3
2
2
1.5
8
10
2
15
0
24
12
37
40
41
20
20
20
20
10
12
Min
3
-10
Max
10
Min
3
-15
Max
15
Min
3
-25
Max
25
Units
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
See ordering information for valid part numbers and speed grades.
Shaded -25 parts are obsolete with a last-time buy date of August 19, 1999.
Shaded -7 and -15 parts are obsolete with a last-time buy date of September 30, 2006.
4
ATF20V8B(Q)(L)
ATF20V8B(Q)(L)
Input Test Waveforms and
Measurement Levels
Output Test Loads
Commercial
t
R
, t
F
< 5 ns (10% to 90%)
Pin Capacitance
f = 1 MHz, T = 25°C
(1)
Typ
C
IN
C
OUT
Note:
5
6
Max
8
8
Units
pF
pF
Conditions
V
IN
= 0V
V
OUT
= 0V
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power-up Reset
The registers in the ATF20V8Bs are designed to reset dur-
ing power-up. At a point delayed slightly from V
CC
crossing
V
RST
, all registers will be reset to the low state. As a result,
the registered output state will always be high on power-up.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how V
CC
actually rises in the system, the fol-
lowing conditions are required:
1. The V
CC
rise must be monotonic,
2. After reset occurs, all input and feedback setup
times must be met before driving the clock pin high,
and
3. The clock must remain stable during t
PR
.
Parameter
t
PR
V
RST
Description
Power-up Reset Time
Power-up Reset Voltage
Typ
600
3.8
Max
1,000
4.5
Units
ns
V
Preload of Registered Outputs
The ATF16V8B’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC file
preload sequence will be done automatically by most of the
approved programmers after the programming.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF20V8B fuse patterns. Once programmed, fuse
verify and preload are inhibited. However, the 64-bit User
Signature remains accessible.
The security fuse should be programmed last, as its effect
is immediate.
Electronic Signature Word
There are 64 bits of programmable memory that are always
available to the user, even if the device is secured. These
bits can be used for user-specific data.
Programming/Erasing
Programming/erasing is performed using standard PLD
programmers. For further information, see the Configurable
Logic Databook, section titled, “CMOS PLD Programming
Hardware and Software Support.”
5
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