LPC2458
Single-chip 16-bit/32-bit micro; 512 kB flash, Ethernet, CAN,
ISP/IAP, USB 2.0 device/host/OTG, external memory interface
Rev. 4.1 — 15 October 2013
Product data sheet
1. General description
NXP Semiconductors designed the LPC2458 microcontroller around a 16-bit/32-bit
ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and
embedded trace. The LPC2458 has 512 kB of on-chip high-speed flash memory. This
flash memory includes a special 128-bit wide memory interface and accelerator
architecture that enables the CPU to execute sequential instructions from flash memory at
the maximum 72 MHz system clock rate. This feature is available only on the LPC2000
ARM microcontroller family of products. The LPC2458 can execute both 32-bit ARM and
16-bit Thumb instructions. Support for the two instruction sets means engineers can
choose to optimize their application for either performance or code size at the sub-routine
level. When the core executes instructions in Thumb state it can reduce code size by
more than 30 % with only a small loss in performance while executing instructions in ARM
state maximizes core performance.
The LPC2458 microcontroller is ideal for multi-purpose communication applications. It
incorporates a 10/100 Ethernet Media Access Controller (MAC), a USB full-speed
Device/Host/OTG Controller with 4 kB of endpoint RAM, four UARTs, two Controller Area
Network (CAN) channels, an SPI interface, two Synchronous Serial Ports (SSP), three I
2
C
interfaces, and an I
2
S interface. Supporting this collection of serial communications
interfaces are the following feature components; an on-chip 4 MHz internal precision
oscillator, 98 kB of total RAM consisting of 64 kB of local SRAM, 16 kB SRAM for
Ethernet, 16 kB SRAM for general purpose DMA, 2 kB of battery powered SRAM, and an
External Memory Controller (EMC). These features make this device optimally suited for
communication gateways and protocol converters. Complementing the many serial
communication controllers, versatile clocking capabilities, and memory features are
various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, two PWM units, four external
interrupt pins, and up to 136 fast GPIO lines. The LPC2458 connects 64 of the GPIO pins
to the hardware based Vector Interrupt Controller (VIC) that means these external inputs
can generate edge-triggered interrupts. All of these features make the LPC2458
particularly suitable for industrial control and medical systems.
2. Features and benefits
ARM7TDMI-S processor, running at up to 72 MHz.
512 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. Flash program memory is on the ARM
local bus for high performance CPU access.
98 kB on-chip SRAM includes:
64 kB of SRAM on the ARM local bus for high performance CPU access.
16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
NXP Semiconductors
LPC2458
Single-chip 16-bit/32-bit micro
16 kB SRAM for general purpose DMA use also accessible by the USB.
2 kB SRAM data storage powered from the Real-Time Clock (RTC) power domain.
Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet
DMA, USB DMA, and program execution from on-chip flash with no contention.
EMC provides support for asynchronous static memory devices such as RAM, ROM
and flash, as well as dynamic memories such as Single Data Rate SDRAM.
Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP,
I
2
S, and SD/MM interface as well as for memory-to-memory transfers.
Serial Interfaces:
Ethernet MAC with MII/RMII interface and associated DMA controller. These
functions reside on an independent AHB.
USB 2.0 full-speed dual port Device/Host/OTG Controller with on-chip PHY and
associated DMA controller.
Four UARTs with fractional baud rate generation, one with modem control I/O, one
with IrDA support, all with FIFO.
CAN controller with two channels.
SPI controller.
Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate
for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA controller.
Three I
2
C-bus interfaces (one with open-drain and two with standard port pins).
I
2
S (Inter-IC Sound) interface for digital audio input or output. It can be used with
the GPDMA.
Other peripherals:
SD/MMC memory card interface.
136 General purpose I/O pins with configurable pull-up/down resistors.
10-bit ADC with input multiplexing among 8 pins.
10-bit DAC.
Four general purpose timers/counters with 8 capture inputs and 10 compare
outputs. Each timer block has an external count input.
Two PWM/timer blocks with support for three-phase motor control. Each PWM has
an external count inputs.
RTC with separate power domain, clock source can be the RTC oscillator or the
APB clock.
2 kB SRAM powered from the RTC power pin, allowing data to be stored when the
rest of the chip is powered off.
WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,
the RTC oscillator, or the APB clock.
Standard ARM test/debug interface for compatibility with existing tools.
Emulation trace module supports real-time trace.
Single 3.3 V power supply (3.0 V to 3.6 V).
Four reduced power modes: idle, sleep, power-down, and deep power-down.
Four external interrupt inputs configurable as edge/level sensitive. All pins on port 0
and port 2 can be used as edge sensitive interrupt sources.
Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet
wake-up interrupt, CAN bus activity, port 0/2 pin interrupt).
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
LPC2458
Product data sheet
Rev. 4.1 — 15 October 2013
2 of 81
NXP Semiconductors
LPC2458
Single-chip 16-bit/32-bit micro
Two independent power domains allow fine tuning of power consumption based on
needed features.
Each peripheral has its own clock divider for further power saving. These dividers help
reduce active power by 20 % to 30 %.
Brownout detect with separate thresholds for interrupt and forced reset.
On-chip power-on reset.
On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.
4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as
the system clock. When used as the CPU clock, does not allow CAN and USB to run.
On-chip PLL allows CPU operation up to the maximum CPU rate without the need for
a high frequency crystal. May be run from the main oscillator, the internal RC oscillator,
or the RTC oscillator.
Boundary scan for simplified board testing.
Versatile pin function selections allow more possibilities for using on-chip peripheral
functions.
3. Applications
Industrial control
Medical systems
Protocol converter
Communications
4. Ordering information
Table 1.
Ordering information
Package
Name
Description
Version
SOT570-3
Type number
LPC2458FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12
12
0.8 mm
4.1 Ordering options
Table 2.
Ordering options
Flash
(kB)
Local bus
SRAM (kB)
Ethernet buffer
External
bus
Ethernet
USB
OTG/
OHC/
DEV
+ 4 kB
FIFO
SD/
MMC
CAN channels
GP
DMA
ADC channels
DAC channels
1
40 C
to
+85
C
Temp
range
Type number
GP/USB
LPC2458FET180
512
64 16 16 2
98 16-bit
Total
RTC
MII/
RMII
yes
2
yes
yes
8
LPC2458
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4.1 — 15 October 2013
3 of 81
NXP Semiconductors
LPC2458
Single-chip 16-bit/32-bit micro
5. Block diagram
XTAL1
V
DD(3V3)
XTAL2
V
DDA
TMS TDI
trace signals
TRST
TCK TDO
EXTIN0 DBGEN
RESET
VREF
V
SSA
, V
SSIO,
V
SSCORE
V
DD(DCDC)(3V3)
TEST/DEBUG
INTERFACE
EMULATION
TRACE MODULE
P0, P1, P2,
P3, P4
LPC2458
64 kB
SRAM
512 kB
FLASH
PLL
system
clock
SYSTEM
FUNCTIONS
INTERNAL RC
OSCILLATOR
HIGH-SPEED
GPIO
136 PINS
TOTAL
INTERNAL
CONTROLLERS
SRAM FLASH
ARM7TDMI-S
VIC
16 kB
SRAM
EXTERNAL
MEMORY
CONTROLLER
AHB1
D[15:0]
A[19:0]
control lines
AHB2
AHB
BRIDGE
AHB
BRIDGE
USB DEVICE/
HOST/OTG WITH
4 kB RAM AND DMA
GPDMA
CONTROLLER
I2SRX_CLK
I2STX_CLK
I2SRX_WS
I2STX_WS
I2SRX_SDA
I2STX_SDA
SCK, SCK0
MOSI, MOSI0
MISO, MISO0
SSEL, SSEL0
SCK1
MOSI1
MISO1
SSEL1
MCICLK, MCIPWR
MCICMD,
MCIDAT[3:0]
TXD0, TXD2, TXD3
RXD0, RXD2, RXD3
TXD1
RXD1
DTR1, RTS1
DSR1, CTS1, DCD1,
RI1
CAN1, CAN2
RD1, RD2
TD1, TD2
SCL0, SCL1, SCL2
SDA0, SDA1, SDA2
V
BUS
port 1
port 2
MII/RMII
ETHERNET
MAC WITH
DMA
16 kB
SRAM
MASTER AHB TO SLAVE
PORT AHB BRIDGE PORT
AHB TO
APB BRIDGE
EINT3 to EINT0
P0, P2
2
×
CAP0/CAP1/
CAP2/CAP3
4
×
MAT2,
2
×
MAT3,
2
×
MAT1/MAT0
6
×
PWM0, PWM1
1
×
PCAP0,
2
×
PCAP1
P0, P1
EXTERNAL INTERRUPTS
CAPTURE/COMPARE
TIMER0/TIMER1/
TIMER2/TIMER3
I
2
S INTERFACE
SPI, SSP0 INTERFACE
PWM0, PWM1
LEGACY GPI/O
64 PINS TOTAL
SSP1 INTERFACE
8
×
AD0
A/D CONVERTER
SD/MMC CARD
INTERFACE
AOUT
VBAT
power domain 2
RTCX1
RTCX2
ALARM
D/A CONVERTER
UART0, UART2, UART3
2 kB BATTERY RAM
UART1
RTC
OSCILLATOR
REAL-
TIME
CLOCK
WATCHDOG TIMER
I
2
C0, I
2
C1, I
2
C2
SYSTEM CONTROL
002aad093
Fig 1.
LPC2458 block diagram
LPC2458
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4.1 — 15 October 2013
4 of 81
NXP Semiconductors
LPC2458
Single-chip 16-bit/32-bit micro
6. Pinning information
6.1 Pinning
ball A1
index area
LPC2458
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
002aad094
Transparent top view
Fig 2.
Table 3.
Row A
1
5
P3[12]/D12
P1[1]/ENET_TXD1
2
6
Pin allocation table
LPC2458 pinning TFBGA180 package
Pin Symbol
Pin Symbol
P3[2]/D2
P3[8]/D8
Pin Symbol
3
7
P0[3]/RXD0
P1[10]/ENET_RXD1
Pin Symbol
4
8
P3[9]/D9
P1[15]/
ENET_REF_CLK/
ENET_RX_CLK
P1[11]/ENET_RXD2/
MCIDAT2/PWM0[6]
-
9
13
P1[3]/ENET_TXD3/
MCICMD/PWM0[2]
P0[9]/I2STX_SDA/
MOSI1/MAT2[3]
TDO
P1[0]/ENET_TXD0
P4[29]/
MAT2[1]/RXD3
P1[5]/ENET_TX_ER/
MCIPWR/PWM0[3]
P3[13]/D13
V
DD(3V3)
P1[17]/ENET_MDIO
10
14
V
SSCORE
P1[12]/ENET_RXD3/
MCIDAT3/PCAP0[0]
P3[11]/D11
P1[8]/ENET_CRS_DV/
ENET_CRS
P1[6]/ENET_TX_CLK/
MCIDAT0/PWM0[4]
P4[13]/A13
11
15
P0[4]/I2SRX_CLK/RD2/ 12
CAP2[0]
-
16
Row B
1
5
9
13
2
6
10
14
3
7
11
15
P3[10]/D10
P1[2]/ENET_TXD2/
MCICLK/PWM0[1]
P0[5]/I2SRX_WS/TD2/
CAP2[1]
-
4
8
12
16
V
SSIO
P1[16]/ENET_MDC
P0[7]/I2STX_CLK/SCK1
/MAT2[1]
-
Row C
1
5
9
2
6
10
TMS
P1[4]/ENET_TX_EN
P4[15]/A15
3
7
11
TDI
P4[30]/CS0
V
SSIO
4
8
12
RTCK
P4[24]/OE
P0[8]/I2STX_WS/
MISO1/MAT2[2]
LPC2458
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4.1 — 15 October 2013
5 of 81
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