INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT390
Dual decade ripple counter
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Dual decade ripple counter
FEATURES
•
Two BCD decade or bi-quinary counters
•
One package can be configured to divide-by-2, 4, 5, 10,
20, 25, 50 or 100
•
Two master reset inputs to clear each decade counter
individually
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT390 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT390 are dual 4-bit decade ripple counters
divided into four separately clocked sections. The counters
have two divide-by-2 sections and two divide-by-5
sections. These sections are normally used in a BCD
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT390
decade or bi-quinary configuration, since they share a
common master reset input (nMR). If the two master reset
inputs (1MR and 2MR) are used to simultaneously clear all
8 bits of the counter, a number of counting configurations
are possible within one package. The separate clocks
(nCP
0
and nCP
1
) of each section allow ripple counter or
frequency division applications of divide-by-2, 4, 5, 10, 20,
25, 50 or 100.
Each section is triggered by the HIGH-to-LOW transition of
the clock inputs (nCP
0
and nCP
1
). For BCD decade
operation, the nQ
0
output is connected to the nCP
1
input
of, the divide-by-5 section. For bi-quinary decade
operation, the nQ
3
output is connected to the nCP
0
input
and nQ
0
becomes the decade output.
The master reset inputs (1MR and 2MR) are active HIGH
asynchronous inputs to each decade counter which
operates on the portion of the counter identified by the “1”
and “2” prefixes in the pin configuration. A HIGH level on
the nMR input overrides the clocks and sets the four
outputs LOW.
TYPICAL
SYMBOL
t
PHL
/ t
PLH
PARAMETER
propagation delay
nCP
0
to nQ
0
nCP
1
to nQ
1
nCP
1
to nQ
2
nCP
1
to nQ
3
nMR to Q
n
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−1.5
V
maximum clock frequency nCP
0
, nCP
1
input capacitance
power dissipation capacitance per counter
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
14
15
23
15
16
66
3.5
20
18
19
26
19
18
61
3.5
21
ns
ns
ns
ns
ns
MHz
pF
pF
HCT
UNIT
December 1990
2
Philips Semiconductors
Product specification
Dual decade ripple counter
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL
PARAMETER
+25
−40
to
+85
−40
to
+125
max.
220
44
38
235
47
40
315
63
54
235
47
40
250
50
43
110
22
19
120
24
20
130
26
22
110
22
19
4.0
20
24
ns
74HC/HCT390
TEST CONDITIONS
UNIT V
WAVEFORMS
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.6
min. typ. max. min. max. min.
t
PHL
/ t
PLH
propagation delay
nCP
0
to nQ
0
propagation delay
nCP
1
to nQ
1
propagation delay
nCP
1
to nQ
2
propagation delay
nCP
1
to nQ
3
propagation delay
nMR to nQ
n
output transition time
47
17
14
50
18
14
74
27
22
50
18
14
52
19
15
19
7
6
80
16
14
80
17
14
75
15
13
6.0
30
35
19
7
6
28
10
8
22
8
6
20
60
71
145
29
25
155
31
26
210
42
36
155
31
26
165
33
28
75
15
13
100
20
17
105
21
18
95
19
16
4.8
24
28
180
36
31
195
39
33
265
53
45
195
39
33
205
41
35
95
19
16
t
PHL
/ t
PLH
ns
Fig.6
t
PHL
/ t
PLH
ns
Fig.6
t
PHL
/ t
PLH
ns
Fig.6
t
PHL
ns
Fig.7
t
THL
/ t
TLH
ns
Fig.6
t
W
clock pulse width
nCP
0
, nCP
1
master reset pulse width
HIGH
removal time
nMR to nCP
n
maximum clock pulse
frequency
nCP
0
, nCP
1
ns
Fig.6
t
W
ns
Fig.7
t
rem
ns
Fig.7
f
max
MHz
Fig.6
December 1990
5
Embedded System
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