82V2044EPFG datasheet, PDF - EEWORLD Datasheet

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82V2044EPFG: DescriptionTelecom Interface ICs OCTAL LH LIU; Categorysemiconductor Analog mixed-signal IC; File Size1MB，73 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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Telecom Interface ICs OCTAL LH LIU

82V2044EPFG Parametric

Parameter Name	Attribute value
Product Category	Telecom Interface ICs
Manufacturer	IDT (Integrated Device Technology, Inc.)
RoHS	Details
Product	LIU - Line Interface Units
Operating Supply Voltage	3.3 V
Operating Supply Current	-
Maximum Operating Temperature	+ 85 C
Mounting Style	SMD/SMT
Package / Case	TQFP-128
Packaging	Tray
Interface Type	Parallel, Serial, JTAG
Minimum Operating Temperature	- 40 C
Number of Channels	4 Channel
Number of Input Lines	4 Line
Pd - Power Dissipation	1.69 W
Factory Pack Quantity	15
Supply Voltage - Max	3.47 V
Supply Voltage - Min	3.13 V
Type	T1/E1/J1 Short Haul Line Interface
Unit Weight	0.017760 oz

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QUAD CHANNEL T1/E1/J1

SHORT HAUL LINE INTERFACE UNIT

IDT82V2044E

FEATURES:

•

Four channel T1/E1/J1 short haul line interfaces

Supports HPS (Hitless Protection Switching) for 1+1 protection

without external relays

Programmable T1/E1/J1 switchability allowing one bill of ma-

terial for any line condition

Single 3.3 V power supply with 5 V tolerance on digital interfaces

Meets or exceeds specifications in

ANSI T1.102, T1.403 and T1.408

- ITU I.431, G.703,G.736, G.775 and G.823

- ETSI 300-166, 300-233 and TBR 12/13

- AT&T Pub 62411

Per channel software selectable on:

- Wave-shaping templates

- Line terminating impedance (T1:100

Ω,

J1:110

Ω,

E1:75

Ω/120 Ω)

- Adjustment of arbitrary pulse shape

- JA (Jitter Attenuator) position (receive path or transmit path)

- Single rail/dual rail system interfaces

B8ZS/HDB3/AMI line encoding/decoding

- Active edge of transmit clock (TCLK) and receive clock (RCLK)

- Active level of transmit data (TDATA) and receive data (RDATA)

- Receiver or transmitter power down

- High impedance setting for line drivers

- PRBS (Pseudo Random Bit Sequence) generation and detection

with 2

-1 PRBS polynomials for E1

- QRSS (Quasi Random Sequence Signals) generation and detection

with 2

-1 QRSS polynomials for T1/J1

- 16-bit BPV (Bipolar Pulse Violation)/Excess Zero/PRBS or QRSS

error counter

- Analog loopback, Digital loopback, Remote loopback and Inband

loopback

Adaptive receive sensitivity up to -20 dB

Non-intrusive monitoring per ITU G.772 specification

Short circuit protection for line drivers

LOS (Loss Of Signal) detection with programmable LOS levels

AIS (Alarm Indication Signal) detection

JTAG interface

Supports serial control interface, Motorola and Intel Non-Multi-

plexed interfaces

Package:

IDT82V2044E: 128-pin TQFP

•

DESCRIPTION:

The IDT82V2044E can be configured as a quad T1, quad E1 or quad

J1 Line Interface Unit. The IDT82V2044E performs clock/data recovery,

AMI/B8ZS/HDB3 line decoding and detects and reports the LOS condi-

tions. An integrated Adaptive Equalizer is available to increase the receive

sensitivity and enable programming of LOS levels. In transmit path, there

is an AMI/B8ZS/HDB3 encoder and Waveform Shaper. There is one Jitter

Attenuator for each channel, which can be placed in either the receive path

or the transmit path. The Jitter Attenuator can also be disabled. The

IDT82V2044E supports both Single Rail and Dual Rail system interfaces

and both serial and parallel control interfaces. To facilitate the network

maintenance, a PRBS/QRSS generation/detection circuit is integrated in

each channel, and different types of loopbacks can be set on a per channel

basis. Four different kinds of line terminating impedance, 75Ω, 100

Ω,

110

Ω

and 120

Ω

are selectable on a per channel basis. The chip also provides

driver short-circuit protection and supports JTAG boundary scanning.

The IDT82V2044E can be used in SDH/SONET, LAN, WAN, Routers,

Wireless Base Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay

Access Devices, CSU/DSU equipment, etc.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGES

August 2004

DSC-6533/-



QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL

TEMPERATURE RANGES

TABLE OF CONTENTS

IDT82V2044E PIN CONFIGURATIONS ....................................................................................... 8

PIN DESCRIPTION ....................................................................................................................... 9

FUNCTIONAL DESCRIPTION .................................................................................................... 14

3.1

T1/E1/J1 MODE SELECTION .......................................................................................... 14

3.2

TRANSMIT PATH ............................................................................................................. 14

3.2.1 TRANSMIT PATH SYSTEM INTERFACE.............................................................. 14

3.2.2 ENCODER .............................................................................................................. 14

3.2.3 PULSE SHAPER .................................................................................................... 14

3.2.3.1 Preset Pulse Templates .......................................................................... 14

3.2.3.2 User-Programmable Arbitrary Waveform ................................................ 15

3.2.4 TRANSMIT PATH LINE INTERFACE..................................................................... 18

3.2.5 TRANSMIT PATH POWER DOWN ........................................................................ 18

3.3

RECEIVE PATH ............................................................................................................... 19

3.3.1 RECEIVE INTERNAL TERMINATION.................................................................... 19

3.3.2 LINE MONITOR ...................................................................................................... 20

3.3.3 ADAPTIVE EQUALIZER......................................................................................... 20

3.3.4 RECEIVE SENSITIVITY ......................................................................................... 20

3.3.5 DATA SLICER ........................................................................................................ 20

3.3.6 CDR (Clock & Data Recovery)................................................................................ 20

3.3.7 DECODER .............................................................................................................. 20

3.3.8 RECEIVE PATH SYSTEM INTERFACE ................................................................ 20

3.3.9 RECEIVE PATH POWER DOWN........................................................................... 20

3.3.10 G.772 NON-INTRUSIVE MONITORING ................................................................ 21

3.4

JITTER ATTENUATOR .................................................................................................... 22

3.4.1 JITTER ATTENUATION FUNCTION DESCRIPTION ............................................ 22

3.4.2 JITTER ATTENUATOR PERFORMANCE ............................................................. 22

3.5

LOS AND AIS DETECTION ............................................................................................. 23

3.5.1 LOS DETECTION ................................................................................................... 23

3.5.2 AIS DETECTION .................................................................................................... 24

3.6

TRANSMIT AND DETECT INTERNAL PATTERNS ........................................................ 25

3.6.1 TRANSMIT ALL ONES ........................................................................................... 25

3.6.2 TRANSMIT ALL ZEROS......................................................................................... 25

3.6.3 PRBS/QRSS GENERATION AND DETECTION.................................................... 25

3.7

LOOPBACK ...................................................................................................................... 25

3.7.1 ANALOG LOOPBACK ............................................................................................ 25

3.7.2 DIGITAL LOOPBACK ............................................................................................. 25

3.7.3 REMOTE LOOPBACK............................................................................................ 25

3.7.4 INBAND LOOPBACK.............................................................................................. 27

3.7.4.1 Transmit Activate/Deactivate Loopback Code......................................... 27

3.7.4.2 Receive Activate/Deactivate Loopback Code.......................................... 27

3.7.4.3 Automatic Remote Loopback .................................................................. 27

3.8

ERROR DETECTION/COUNTING AND INSERTION ...................................................... 28

QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL

TEMPERATURE RANGES

3.9

3.10

3.11

3.12

3.13

3.14

3.15

3.8.1 DEFINITION OF LINE CODING ERROR ............................................................... 28

3.8.2 ERROR DETECTION AND COUNTING ................................................................ 28

3.8.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 29

LINE DRIVER FAILURE MONITORING ........................................................................... 29

MCLK AND TCLK ............................................................................................................. 30

3.10.1 MASTER CLOCK (MCLK) ...................................................................................... 30

3.10.2 TRANSMIT CLOCK (TCLK).................................................................................... 30

MICROCONTROLLER INTERFACES ............................................................................. 31

3.11.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 31

3.11.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 31

INTERRUPT HANDLING .................................................................................................. 32

5V TOLERANT I/O PINS .................................................................................................. 32

RESET OPERATION ........................................................................................................ 32

POWER SUPPLY ............................................................................................................. 32

PROGRAMMING INFORMATION .............................................................................................. 33

4.1

4.2

4.2.1 GLOBAL REGISTERS............................................................................................ 35

4.2.2 JITTER ATTENUATION CONTROL REGISTER ................................................... 37

4.2.3 TRANSMIT PATH CONTROL REGISTERS........................................................... 38

4.2.4 RECEIVE PATH CONTROL REGISTERS ............................................................. 40

4.2.5 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 42

4.2.6 INTERRUPT CONTROL REGISTERS ................................................................... 45

4.2.7 LINE STATUS REGISTERS ................................................................................... 47

4.2.8 INTERRUPT STATUS REGISTERS ...................................................................... 49

4.2.9 COUNTER REGISTERS ........................................................................................ 50

4.2.10 TRANSMIT AND RECEIVE TERMINATION REGISTER ....................................... 51

IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 52

5.1

JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 53

5.2

JTAG DATA REGISTER ................................................................................................... 53

5.2.1 DEVICE IDENTIFICATION REGISTER (IDR) ........................................................ 53

5.2.2 BYPASS REGISTER (BR)...................................................................................... 53

5.2.3 BOUNDARY SCAN REGISTER (BSR) .................................................................. 53

5.2.4 TEST ACCESS PORT CONTROLLER .................................................................. 54

TEST SPECIFICATIONS ............................................................................................................ 56

MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 68

7.1

SERIAL INTERFACE TIMING .......................................................................................... 68

7.2

PARALLEL INTERFACE TIMING ..................................................................................... 69

QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL

TEMPERATURE RANGES

LIST OF TABLES

Table-1

Table-2

Table-3

Table-4

Table-5

Table-6

Table-7

Table-8

Table-9

Table-10

Table-11

Table-12

Table-13

Table-14

Table-15

Table-16

Table-17

Table-18

Table-19

Table-20

Table-21

Table-22

Table-23

Table-24

Table-25

Table-26

Table-27

Table-28

Table-29

Table-30

Table-31

Table-32

Table-33

Table-34

Table-35

Table-36

Table-37

Table-38

Table-39

Table-40

Pin Description ................................................................................................................ 9

Transmit Waveform Value For E1 75

Ω

........................................................................ 15

Transmit Waveform Value For E1 120

Ω

...................................................................... 16

Transmit Waveform Value For T1 0~133 ft................................................................... 16

Transmit Waveform Value For T1 133~266 ft............................................................... 16

Transmit Waveform Value For T1 266~399 ft............................................................... 16

Transmit Waveform Value For T1 399~533 ft............................................................... 17

Transmit Waveform Value For T1 533~655 ft............................................................... 17

Transmit Waveform Value For J1 0~655 ft ................................................................... 17

Impedance Matching for Transmitter ............................................................................ 18

Impedance Matching for Receiver ................................................................................ 19

Criteria of Starting Speed Adjustment........................................................................... 22

LOS Declare and Clear Criteria, Adaptive Equalizer Disabled ..................................... 23

LOS Declare and Clear Criteria, Adaptive Equalizer Enabled ...................................... 24

AIS Condition ................................................................................................................ 24

Criteria for Setting/Clearing the PRBS_S Bit ................................................................ 25

EXZ Definition ............................................................................................................... 28

Interrupt Event............................................................................................................... 32

Global Register List and Map........................................................................................ 33

Per Channel Register List and Map .............................................................................. 34

ID: Chip Revision Register ............................................................................................ 35

RST: Reset Register ..................................................................................................... 35

GCF0: Global Configuration Register 0 ........................................................................ 35

GCF1: Global Configuration Register 1 ........................................................................ 36

INTCH: Interrupt Channel Indication Register............................................................... 36

JACF: Jitter Attenuator Configuration Register ............................................................. 37

TCF0: Transmitter Configuration Register 0 ................................................................. 38

TCF1: Transmitter Configuration Register 1 ................................................................. 38

TCF2: Transmitter Configuration Register 2 ................................................................. 39

TCF3: Transmitter Configuration Register 3 ................................................................. 39

TCF4: Transmitter Configuration Register 4 ................................................................. 39

RCF0: Receiver Configuration Register 0..................................................................... 40

RCF1: Receiver Configuration Register 1..................................................................... 40

RCF2: Receiver Configuration Register 2..................................................................... 41

MAINT0: Maintenance Function Control Register 0...................................................... 42

MAINT1: Maintenance Function Control Register 1...................................................... 42

MAINT2: Maintenance Function Control Register 2...................................................... 43

MAINT3: Maintenance Function Control Register 3...................................................... 43

MAINT4: Maintenance Function Control Register 4...................................................... 43

MAINT5: Maintenance Function Control Register 5...................................................... 43

82V2044EPFG Related Products

	82V2044EPFG	82V2044EPF8
Description	Telecom Interface ICs OCTAL LH LIU	Telecom Interface ICs OCTAL LH LIU
Product Category	Telecom Interface ICs	Telecom Interface ICs
Manufacturer	IDT (Integrated Device Technology, Inc.)	IDT (Integrated Device Technology, Inc.)
RoHS	Details	No
Product	LIU - Line Interface Units	LIU - Line Interface Units
Operating Supply Voltage	3.3 V	3.3 V
Maximum Operating Temperature	+ 85 C	+ 85 C
Mounting Style	SMD/SMT	SMD/SMT
Package / Case	TQFP-128	TQFP-128
Packaging	Tray	Reel
Interface Type	Parallel, Serial, JTAG	Parallel, Serial, JTAG
Minimum Operating Temperature	- 40 C	- 40 C
Number of Channels	4 Channel	4 Channel
Number of Input Lines	4 Line	4 Line
Pd - Power Dissipation	1.69 W	1.69 W
Factory Pack Quantity	15	1000
Supply Voltage - Max	3.47 V	3.47 V
Supply Voltage - Min	3.13 V	3.13 V
Type	T1/E1/J1 Short Haul Line Interface	T1/E1/J1 Short Haul Line Interface
Unit Weight	0.017760 oz	0.017760 oz

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