• SerDes associated with unused ports are turned-off
• SerDes associated with unused lanes are placed in a low
power state
9 General Purpose I/O
Reliability, Availability and Serviceability (RAS)
ECRC support
AER on all ports
SECDED ECC protection on all internal RAMs
End-to-end data path parity protection
Checksum Serial EEPROM content protected
Autonomous link reliability (preserves system operation in the
presence of faulty links)
–
Ability to generate an interrupt (INTx or MSI) on link up/down
transitions
Test and Debug
–
On-chip link activity and status outputs available for Port 0
(upstream port)
–
Per port link activity and status outputs available using
external I
2
C I/O expander for all other ports
–
SerDes test modes
–
Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG
Power Supplies
–
Requires only two power supply voltages (1.0 V and 2.5 V)
Note that a 3.3V is preferred for V
DD
I/O
–
No power sequencing requirements
Packaged in a 27mm x 27mm 676-ball Flip Chip BGA with
1mm ball spacing
–
–
–
–
–
–
Product Description
Utilizing standard PCI Express Gen2 interconnect, the
PES48H12G2 provides the most efficient system interconnect switching
solution for applications requiring high throughput, low latency, and
simple board layout with a minimum number of board layers. It provides
48 GBps (384 Gbps) of aggregated, full-duplex switching capacity
through 48 integrated serial lanes, using proven and robust IDT tech-
nology. Each lane is capable of 5 GT/s of bandwidth in both directions
and is fully compliant with PCI Express Base specification 2.0.
The PES48H12G2 is based on a flexible and efficient layered archi-
tecture. The PCI Express layer consists of SerDes, Physical, Data Link
and Transaction layers in compliance with PCI Express Base specifica-
tion Revision 2.0. The PES48H12G2 can operate either as a store and
forward or cut-through switch. It supports eight Traffic Classes (TCs)
and one Virtual Channel (VC) with sophisticated resource management
to enable efficient switching and I/O connectivity for servers, storage,
and embedded processors with limited connectivity.
The PES48H12G2 is a
partitionable
PCIe switch. This means that in
addition to operating as a standard PCI express switch, the
PES48H12G2 ports may be partitioned into groups that logically
operate as completely independent PCIe switches. Figure 2 illustrates a
three partition PES48H12G2 configuration.
2 of 44
November 28, 2011
IDT 89HPES48H12G2 Data Sheet
Block Diagram
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
Route Table
Port
Arbitration
12-Port Switch Core
Frame Buffer
Scheduler
DL/Transaction Layer
DL/Transaction Layer
DL/Transaction Layer
SerDes
SerDes
SerDes
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
48 PCI Express Lanes
Up to 6 x8 ports or 12 x4 Ports
Figure 1 Internal Block Diagram
Partition 1
Upstream Port
Partition 2
Upstream Port
Partition 3
Upstream Port
P2P
Bridge
P2P
Bridge
P2P
Bridge
Partition 1 – Virtual PCI Bus
Partition 2 – Virtual PCI Bus
Partition 3 – Virtual PCI Bus
P2P
Bridge
P2P
Bridge
P2P
Bridge
P2P
Bridge
P2P
Bridge
P2P
Bridge
P2P
Bridge
P2P
Bridge
Partition 1
Downstream Ports
Partition 2
Downstream Ports
Partition 3
Downstream Ports
Figure 2 Example of Usage of Switch Partitioning
3 of 44
November 28, 2011
IDT 89HPES48H12G2 Data Sheet
SMBus Interface
The PES48H12G2 contains an SMBus master interface. This master interface allows the default configuration register values of the PES48H12G2
to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug
I/O expander. Two pins make up the SMBus master interface: an SMBus clock pin and an SMBus data pin. Four pins make up the SMBus slave inter-
face: an SMBus clock pin and an SMBus data pin plus two address pins, SSMBADDR[2,1].
As shown in Figure 3, the master and slave SMBuses may only be used in a split configuration.
Switch
Processor
SMBus
Master
...
Other
SMBus
Devices
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
Serial
EEPROM
Hot-Plug
I/O
Expander
Figure 3 Split SMBus Interface Configuration
The switch’s SMBus master interface does not support SMBus arbitration. As a result, the switch’s SMBus master must be the only master in the
SMBus lines that connect to the serial EEPROM and I/O expander slaves. In the split configuration, the master and slave SMBuses operate as two
independent buses; thus, multi-master arbitration is not required.
Hot-Plug Interface
The PES48H12G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the
PES48H12G2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset
and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES48H12G2 generates an SMBus transaction to the I/O
expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on
the IOEXPINTN input pin (alternate function of GPIO) of the PES48H12G2. In response to an I/O expander interrupt, the PES48H12G2 generates an
SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES48H12G2 provides 9 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin
may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These
alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
Pin Description
The following tables list the functions of the pins provided on the PES48H12G2. Some of the functions listed may be multiplexed onto the same
pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero
(low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
4 of 44
November 28, 2011
IDT 89HPES48H12G2 Data Sheet
Signal
PE00RP[3:0]
PE00RN[3:0]
PE00TP[3:0]
PE00TN[3:0]
PE01RP[3:0]
PE01RN[3:0]
PE01TP[3:0]
PE01TN[3:0]
PE02RP[3:0]
PE02RN[3:0]
PE02TP[3:0]
PE02TN[3:0]
PE03RP[3:0]
PE03RN[3:0]
PE03TP[3:0]
PE03TN[3:0]
PE04RP[3:0]
PE04RN[3:0]
PE04TP[3:0]
PE04TN[3:0]
PE05RP[3:0]
PE05RN[3:0]
PE05TP[3:0]
PE05TN[3:0]
PE06RP[3:0]
PE06RN[3:0]
PE06TP[3:0]
PE06TN[3:0]
PE07RP[3:0]
PE07RN[3:0]
PE07TP[3:0]
PE07TN[3:0]
PE08RP[3:0]
PE08RN[3:0]
PE08TP[3:0]
PE08TN[3:0]
Type
I
O
I
Name/Description
PCI Express Port 0 Serial Data Receive.
Differential PCI Express receive
pairs for port 0.
PCI Express Port 0 Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port 0.
PCI Express Port 1 Serial Data Receive.
Differential PCI Express receive
pairs for port 1. When port 0 is merged with port 1, these signals become
port 0 receive pairs for lanes 4 through 7.
PCI Express Port 1 Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port 1. When port 0 is merged with port 1, these signals
become port 0 transmit pairs for lanes 4 through 7.
PCI Express Port 2 Serial Data Receive.
Differential PCI Express receive
pairs for port 2.
PCI Express Port 2 Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port 2.
PCI Express Port 3 Serial Data Receive.
Differential PCI Express receive
pairs for port 3. When port 2 is merged with port 3, these signals become
port 2 receive pairs for lanes 4 through 7.
PCI Express Port 3 Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port 3. When port 2 is merged with port 3, these signals
become port 2 transmit pairs for lanes 4 through 7.
PCI Express Port 4 Serial Data Receive.
Differential PCI Express receive
pairs for port 4.
PCI Express Port 4 Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port 4.
PCI Express Port 5 Serial Data Receive.
Differential PCI Express receive
pairs for port 5. When port 4 is merged with port 5, these signals become
port 4 receive pairs for lanes 4 through 7.
PCI Express Port 5 Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port 5. When port 4 is merged with port 5, these signals
become port 4 transmit pairs for lanes 4 through 7.
PCI Express Port 6 Serial Data Receive.
Differential PCI Express receive
pairs for port 6.
PCI Express Port 6 Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port 6.
PCI Express Port 7 Serial Data Receive.
Differential PCI Express receive
pairs for port 7. When port 6 is merged with port 7, these signals become
port 6 receive pairs for lanes 4 through 7.
PCI Express Port 7 Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port 7. When port 6 is merged with port 7, these signals
become port 6 transmit pairs for lanes 4 through 7.
京公网安备 11010802033920号
EEWORLD
