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87004AGLFT

Description
Clock Generators u0026 Support Products 4 LVCMOS OUT CLOCK GEN
Categorysemiconductor    Analog mixed-signal IC   
File Size667KB,15 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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87004AGLFT Overview

Clock Generators u0026 Support Products 4 LVCMOS OUT CLOCK GEN

87004AGLFT Parametric

Parameter NameAttribute value
Product CategoryClock Generators & Support Products
ManufacturerIDT (Integrated Device Technology, Inc.)
RoHSDetails
Mounting StyleSMD/SMT
Package / CaseTSSOP-24
PackagingReel
Height1 mm
Length7.8 mm
Factory Pack Quantity3000
Width4.4 mm
Unit Weight0.007478 oz
1:4, Differential-to-LVCMOS/LVTTL
Zero Delay Clock Generator
ICS87004
DATA SHEET
General Description
The ICS87004 is a highly versatile 1:4 Differential-
to-LVCMOS/LVTTL Clock Generator and a member of
HiPerClockS™
the HiPerClockS® family of High Performance Clock
Solutions from IDT. The ICS87004 has two selectable
clock inputs. The CLK0, nCLK0 and CLK1, nCLK1
pairs can accept most standard differential input levels. Internal bias
on the nCLK0 and nCLK1 inputs allows the CLK0 and CLK1 inputs
to accept LVCMOS/LVTTL. The ICS87004 has a fully integrated PLL
and can be configured as zero delay buffer, multiplier or divider and
has an input and output frequency range of 15.625MHz to 250MHz.
The reference divider, feedback divider and output divider are each
programmable, thereby allowing for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external
feedback allows the device to achieve “zero delay” between the input
clock and the output clocks. The PLL_SEL pin can be used to
bypass the PLL for system test and debug purposes. In bypass
mode, the reference clock is routed around the PLL and into the
internal output dividers.
Features
Four LVCMOS/LVTTL outputs, 7
typical output impedance
Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs
CLKx/nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL
levels on CLK0 and CLK1 inputs
Output frequency range: 15.625MHz to 250MHz
Input frequency range: 15.625MHz to 250MHz
VCO range: 250MHz to 500MHz
External feedback for “zero delay” clock regeneration with
configurable frequencies
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Fully integrated PLL
Cycle-to-cycle jitter: 45ps (maximum)
Output skew: 50ps (maximum)
Static phase offset: 50ps ± 125ps (3.3V ± 5%), CLK0/nCLK0
Full 3.3V or 2.5V output operating supply
5V tolerant inputs
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
ICS
Block Diagram
PLL_SEL
Pullup
÷2, ÷4, ÷8, ÷16
÷32, ÷64, ÷128
0
1
1
Q1
Q0
0
Pin Assignment
GND
Q0
V
DDO
SEL0
SEL1
SEL2
SEL3
CLK_SEL
V
DD
CLK0
nCLK0
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Q1
V
DDO
Q2
GND
Q3
V
DDO
MR
FB_IN
PLL_SEL
CLK1
nCLK1
V
DDA
CLK0
Pulldown
nCLK0
Pullup/Pulldown
CLK1
Pulldown
nCLK1
Pullup/Pulldown
CLK_SEL
Pulldown
FB_IN
Pulldown
PLL
Q2
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
Q3
ICS87004
24-Lead TSSOP
7.8mm x 4.4mm x 0.925mm package body
G Package
Top View
SEL0
Pulldown
SEL1
Pulldown
SEL2
Pulldown
SEL3
Pulldown
MR
Pulldown
ICS87004AG REVISION C DECEMBER 1, 2009
1
©2009 Integrated Device Technology, Inc.
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