• Phase-Lock Loop Clock Distribution for Applications ranging
from 10MHz to 133MHz operating frequency
• Distributes one clock input to two banks of four outputs
• Separate output enable for each output bank
• External feedback (FBK) pin is used to synchronize the outputs
to the clock input
• Output Skew <200 ps
• Low jitter <200 ps cycle-to-cycle
• 1x, 2x, 4x output options (see table):
– IDT2308-1 1x
– IDT2308-2 1x, 2x
– IDT2308-3 2x, 4x
– IDT2308-4 2x
– IDT2308-1H, -2H, and -5H for High Drive
• No external RC network required
• Operates at 3.3V V
DD
• Available in SOIC and TSSOP packages
DESCRIPTION:
The IDT2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is
designed to address high-speed clock distribution and multiplication applica-
tions. The zero delay is achieved by aligning the phase between the incoming
clock and the output clock, operable within the range of 10 to 133MHz.
The IDT2308 has two banks of four outputs each that are controlled via two
select addresses. By proper selection of input addresses, both banks can be
put in tri-state mode. In test mode, the PLL is turned off, and the input clock
directly drives the outputs for system testing purposes. In the absence of an
input clock, the IDT2308 enters power down, and the outputs are tri-stated. In
this mode, the device will draw less than 25μA.
The IDT2308 is available in six unique configurations for both pre-
scaling and multiplication of the Input REF Clock. (See available options
table.)
The PLL is closed externally to provide more flexibility by allowing the user
to control the delay between the input clock and the outputs.
The IDT2308 is characterized for both Industrial and Commercial operation.
FUNCTIONAL BLOCK DIAGRAM
(-3, -4)
FBK
REF
16
1
2
(-5)
2
PLL
3
2
CLKA1
CLKA2
14
CLKA3
15
CLKA4
S2
S1
8
9
Control
Logic
(-2, -3)
2
6
CLKB1
7
CLKB2
10
CLKB3
11
CLKB4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c
2016
Integrated Device Technology, Inc.
OCTOBER 2016
DSC 5173/12
IDT2308
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
DD
Rating
Supply Voltage Range
Input Voltage Range (REF)
Input Voltage Range
(except REF)
I
IK
(V
I
< 0)
I
OK
(V
O
< 0 or V
O
> V
DD
)
I
O
(V
O
= 0 to V
DD
)
V
DD
or GND
T
A
= 55°C
(in still air)
(3)
T
STG
Operating
Storage Temperature Range
Commercial Temperature
Range
Industrial Temperature
Range
-40 to +85
°C
–65 to +150
0 to +70
°C
°C
Continuous Current
Maximum Power Dissipation
±100
0.7
mA
W
Input Clamp Current
Terminal Voltage with Respect
to GND (inputs V
IH
2.5, V
IL
2.5)
Continuous Output Current
±50
mA
Max.
–0.5 to +4.6
–0.5 to +5.5
–0.5 to
V
DD
+0.5
–50
±50
mA
mA
Unit
V
V
V
V
I (2)
V
I
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FBK
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
SOIC/ TSSOP
TOP VIEW
Temperature
Operating
Temperature
PIN DESCRIPTION
Pin Number
REF
CLKA1
(1)
CLKA2
(1)
V
DD
GND
CLKB1
(1)
CLKB2
(1)
S2
(2)
Functional Description
Input Reference Clock, 5 Volt Tolerant Input
Clock Output for Bank A
Clock Output for Bank A
3.3V Supply
Ground
Clock Output for Bank B
Clock Output for Bank B
Select Input, Bit 2
Select Input, Bit 1
Clock Output for Bank B
Clock Output for Bank B
Ground
3.3V Supply
Clock Output for Bank A
Clock Output for Bank A
PLL Feedback Input
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150
°
C and a board trace length of 750 mils.
APPLICATIONS:
•
•
•
•
•
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
S1
(2)
CLKB3
(1)
CLKB4
(1)
GND
V
DD
CLKA3
(1)
CLKA4
(1)
FBK
NOTES:
1. Weak pull down on all outputs.
2. Weak pull ups on these inputs.
2
IDT2308
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FUNCTION TABLE
(1)
SELECT INPUT DECODING
S2
L
L
H
H
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
S1
L
H
L
H
CLK A
Tri-State
Driven
Driven
Driven
CLK B
Tri-State
Tri-State
Driven
Driven
Output Source
PLL
PLL
REF
PLL
PLL Shut Down
Y
N
Y
N
AVAILABLE OPTIONS FOR IDT2308
Device
IDT2308-1
IDT2308-1H
IDT2308-2
IDT2308-2
IDT2308-2H
IDT2308-2H
IDT2308-3
IDT2308-3
IDT2308-4
IDT2308-5H
Feedback From
Bank A or Bank B
Bank A or Bank B
Bank A
Bank B
Bank A
Bank B
Bank A
Bank B
Bank A or Bank B
Bank A or Bank B
Bank A Frequency
Reference
Reference
Reference
2 x Reference
Reference
2 x Reference
2 x Reference
4 x Reference
2 x Reference
Reference/2
Bank B Frequency
Reference
Reference
Reference/2
Reference
Reference/2
Reference
Reference or Reference
(1)
2 x Reference
2 x Reference
Reference/2
NOTE:
1. Output phase is indeterminant (0° or 180° from input clock).
3
IDT2308
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ZERO DELAY AND SKEW CONTROL
To close the feedback loop of the IDT2308, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin will
be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust
the input-output delay.
For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay
adjustments are required, use the Output Load Difference Chart to calculate loading differences between the feedback output and remaining outputs.
Ensure the outputs are loaded equally, for zero output-output skew.
REF TO CLKA/CLKB DELAY vs. OUTPUT LOAD DIFFERENCE BETWEEN FBK PIN AND CLKA/CLKB PINS
1500
1000
REF to CLKA/CLKB Delay (ps)
500
0
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
-500
-1000
-1500
OUTPUT LOAD DIFFERENCE BETWEEN FBK PIN AND CLKA/CLKB PINS ( pF)
4
IDT2308
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
OPERATING CONDITIONS- COMMERCIAL
Symbol
V
DD
T
A
C
L
C
IN
Parameter
Supply Voltage
[2]
Operating Temperature (Ambient Temperature)
Load Capacitance below 100MHz
Load Capacitance from 100MHz to 133MHz
Input Capacitance
(1)
NOTES:
1. Applies to both REF and FBK.
2. The IDT2308 requires a monotonic ramp-up of the V
The designed filter is shown in the figure. It is soldered on the FR4 PCB board according to the given value. The 6GHz signal still exists and is not small. Because it is a full board, it is impossibl...
[align=left]Except for the heart rate module and EEPROM, the software part has basically been completed. Therefore, this article mainly discusses the driver implementation of these two parts. [/align]...
Dear experts, I want to use an inverter circuit to amplify a sine wave signal with a peak-to-peak value of 3V and a frequency of 5MHz. The output power is required to reach 10kW. Are there suitable sw...
[b][color=#5E7384]This content is originally created by EEWORLD forum user [size=3]tiankai001[/size]. If you need to reprint or use it for commercial purposes, you must obtain the author's consent and...
10510 The largest one I have ever seen is a 17-chip FPGA, and the 16-chip one is the largest Virtex-5 LX330. Can you imagine such a board? Is it shocking? [/font][size=10.5pt][/size][/size] [size=10.5...
Arrow SoC Kit Each kit includes: Altera cyclone V SOC includes: Built-in dual-core ARM Cortex-A9; 110K LE programmable logic resources High-speed expansion interface (HSMC), and support for 3.125G hig...
Today, with the increasing integration of functions, mobile phones can also be used as portable media players (PMP), digital cameras, handheld computers (PDAs), and even global positioning systems ...[Details]
introduction
Throughout the history of automotive lighting, power has always played an important role. Initially, cars only needed headlights to see the road in the dark. Later, other light so...[Details]
The Portable Digital Data Acquisition System (PDDAS) uses LabVIEW Real-Time and PXI to control the wind tunnel test and record air pressure data from 128 different channels.
"The LabVIEW Real-...[Details]
1 Introduction
With the acceleration of the pace of urban modernization, society has higher requirements for urban road lighting and urban lighting projects. The state has clearly required tha...[Details]
My colleague and I spent the day chatting in the hotel bar. We had met with several customers. We were both wondering how come these engineers we were meeting knew almost nothing about analog techn...[Details]
This paper establishes a fuel cell engine test platform based on the NI integrated hardware and software environment. This platform can realize the test and control of fuel cell engines and their a...[Details]
1. System Structure
This system is a simulation system of indoor air-conditioning temperature/humidity control system. The data acquisition and control center collects temperature/humidity...[Details]
This week, Microsoft held its 2012 Microsoft Worldwide Partner Conference (WPC) in Toronto, Canada. At the conference, Microsoft showed its new products and services to partners around the world. A...[Details]
In the analysis of electronic circuits, static analysis (also known as DC analysis) is the basis of circuit analysis. However, it is well known that electronic components are nonlinear, so the anal...[Details]
RS-422 and RS-485 are both serial data interface standards, which were developed and published by the Electronic Industries Association (EIA). RS-422 defines a balanced communication interface with a ...[Details]
I've been studying dot matrix recently. It looks simple, but it takes a while to master it completely! The 8*8 dot matrix hardware circuit I'm making now is like this. The row is driven by 74HC138 + t...[Details]
Problems such as the depletion of natural resources, air pollution, traffic congestion, and rising fossil fuel prices have forced societies and individuals to seek alternative means of transportati...[Details]
Motors, especially those with brushes, generate a lot of noise. This noise must be dealt with if the appliance is to meet the requirements of EMC standards. The means to solve EMC are nothing more ...[Details]
Describe how to meet the challenges of complexity with a modern wiring design toolset. Option codes and expressions can simulate the variables of an automotive project. A full-featured tool suite c...[Details]
RF/Wirelessly
京公网安备 11010802033920号
EEWORLD
