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Si5330C-B00207-GM

Description
Board to Board u0026 Mezzanine Connectors 44O POS PLUG BRIDGED
Categorysemiconductor    Analog mixed-signal IC   
File Size525KB,20 Pages
ManufacturerSilicon Laboratories
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Si5330C-B00207-GM Overview

Board to Board u0026 Mezzanine Connectors 44O POS PLUG BRIDGED

Si5330C-B00207-GM Parametric

Parameter NameAttribute value
Product CategoryClock Buffer
ManufacturerSilicon Laboratories
RoHSDetails
Number of Outputs4 Output
Maximum Input Frequency250 MHz
Propagation Delay - Max4 ns
Supply Voltage - Max3.63 V
Supply Voltage - Min1.71 V
Maximum Operating Temperature+ 85 C
Minimum Operating Temperature- 40 C
Mounting StyleSMD/SMT
Package / CaseQFN-24
PackagingTray
Duty Cycle - Max60 %
Max Output Freq250 MHz
Operating Supply Current10 mA
Factory Pack Quantity75
Unit Weight0.032741 oz
S i533 0
1 . 8/ 2 .5 /3 .3 V L
O W
-J
I T T E R
, L
O W
-S
K E W
C
L O C K
B
U F F E R
/L
E V E L
T
R A N S L A T O R
Features
Supports single-ended or
differential input clock signals
Generates four differential
(LVPECL, LVDS, HCSL) or eight
single-ended (CMOS, SSTL,
HSTL) outputs
Provides signal level translation

Differential to single-ended

Single-ended to differential

Differential to differential

Single-ended to single-ended
Wide frequency range

LVPECL, LVDS: 5 to 710 MHz

HCSL: 5 to 250 MHz

SSTL, HSTL: 5 to 350 MHz

CMOS: 5 to 200 MHz
Additive jitter: 150 fs RMS typ
Output-output skew: 100 ps
Propagation delay: 2.5 ns typ
Single core supply with excellent
PSRR: 1.8, 2.5, or 3.3 V
Output driver supply voltage
independent of core supply: 1.5,
1.8, 2.5, or 3.3 V
Loss of Signal (LOS) indicator
allows system clock monitoring
Output Enable (OEB) pin allows
glitchless control of output clocks
Low power: 10 mA typical core
current
Industrial temperature range:
–40 to +85
°
C
Small size: 24-lead, 4 x 4 mm
QFN
Ordering Information:
See page 14.
Pin Assignments
Applications
High Speed Clock Distribution
Ethernet Switch/Router
SONET / SDH
PCI Express 2.0/3.0
Fibre Channel
MSAN/DSLAM/PON
Telecom Line Cards
Functional Block Diagram
Rev. 1.2 4/17
Copyright © 2017 by Silicon Laboratories
Si5330
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