EEWORLDEEWORLDEEWORLD

Part Number

Search

5AGXBB3D6F31C6N

Description
FPGA - Field Programmable Gate Array FPGA - Arria V GX 13688 LABs 384 IOs
Categorysemiconductor    Programmable logic devices   
File Size875KB,40 Pages
ManufacturerAltera (Intel)
Download Datasheet Parametric View All

5AGXBB3D6F31C6N Online Shopping

Suppliers Part Number Price MOQ In stock  
5AGXBB3D6F31C6N - - View Buy Now

5AGXBB3D6F31C6N Overview

FPGA - Field Programmable Gate Array FPGA - Arria V GX 13688 LABs 384 IOs

5AGXBB3D6F31C6N Parametric

Parameter NameAttribute value
Product CategoryFPGA - Field Programmable Gate Array
ManufacturerAltera (Intel)
RoHSDetails
ProductArria V GX
Number of Logic Elements362000
Number of Logic Array Blocks - LABs13688
Number of I/Os384 I/O
Operating Supply Voltage850 mV, 1.1 V, 1.15 V
Minimum Operating Temperature0 C
Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT
Package / CaseFBGA-896
PackagingTray
Data Rate3.125 Gb/s
Embedded Block RAM - EBR2098 kbit
Maximum Operating Frequency800 MHz
Number of Transceivers9 Transceiver
Factory Pack Quantity27
Total Memory19358 kbit
2015.12.21
Arria V Device Overview
Subscribe
Send Feedback
AV-51001
The Arria
®
V device family consists of the most comprehensive offerings of mid-range FPGAs ranging
from the lowest power for 6 gigabits per second (Gbps) and 10 Gbps applications, to the highest mid-
range FPGA bandwidth 12.5 Gbps transceivers.
The Arria V devices are ideal for power-sensitive wireless infrastructure equipment, 20G/40G bridging,
switching, and packet processing applications, high-definition video processing and image manipulation,
and intensive digital signal processing (DSP) applications.
Arria V Device Handbook: Known Issues
Lists the planned updates to the Arria V Device Handbook chapters.
Related Information
Key Advantages of Arria V Devices
Table 1: Key Advantages of the Arria V Device Family
Advantage
Supporting Feature
Lowest static power in its
class
• Built on TSMC's 28 nm process technology and includes an abundance of
hard intellectual property (IP) blocks
• Power-optimized MultiTrack routing and core architecture
• Up to 50% lower power consumption than the previous generation
device
• Lowest power transceivers of any midrange family
Improved logic integration • 8-input adaptive logic module (ALM)
and differentiation capabil‐ • Up to 38.38 megabits (Mb) of embedded memory
ities
• Variable-precision digital signal processing (DSP) blocks
Increased bandwidth
capacity
Hard processor system
(HPS) with integrated
ARM
®
Cortex
-A9
MPCore processor
• Serial data rates up to 12.5 Gbps
• Hard memory controllers
• Tight integration of a dual-core ARM Cortex-A9 MPCore processor,
hard IP, and an FPGA in a single Arria V system-on-a-chip (SoC)
• Supports over 128 Gbps peak bandwidth with integrated data coherency
between the processor and the FPGA fabric
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html.
Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
©
ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134
There are rewards for voting in the New Year’s greetings guessing contest!
[font=微软雅黑][size=3][url=https://bbs.eeworld.com.cn/thread-480699-1-1.html]The New Year Greetings Guessing Contest[/url] is coming to an end. We have prepared 20 gifts before the event. Currently, ther...
eric_wang Talking
TPS548D22 Synchronous Buck Converter Supporting 40A Current
1. Features: Converter input voltage: 1.5 V to 16 V Input bias voltage (VDD) range: 4.5 V to 22 V Output voltage range: 0.6 V to 5.5 V -------Integrated 2.9-mΩ and 1.2-mΩ power MOSFETs, can continuous...
dontium Analogue and Mixed Signal
I suggest that the forum should open a special area for graduation theses to facilitate college students to find
I suggest that the forum should open a special area for graduation theses to facilitate college students to find...
heningbo Suggestions & Announcements
Can all EEPROMs be used as 51 external expansion program memory?
The external program memory address of 51 is on port P0 and port P2, so there must be address lines connected to these ports, but what about EEPRIOM without address lines? Can it still be used as exte...
拿得起铁 51mcu
vxworks resolution problem
I now have a vxworks system, which used to run on a special industrial computer, and now I want to run it under a virtual machine. My solution is to regenerate a bsp to boot vxworks, but an error occu...
dafengqixi Real-time operating system RTOS

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2252  449  1972  13  4  46  10  40  1  58 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号