Freescale Semiconductor
Data Sheet: Technical Data
Document Number: IMX51AEC
Rev. 6,
10/2012
IMX51A
i.MX51A Automotive and
Infotainment Applications
Processors
Package Information
Plastic Package
Case 2017 19 x 19 mm, 0.8 mm pitch
Ordering Information
See
Table 1
on
page 2
for ordering information.
1
Introduction
The MCIMX51A (i.MX51A) Automotive Infotainment
Processor represents Freescale Semiconductor’s latest
addition to a growing family of multimedia focused
products offering high performance processing with a
high degree of functional integration, aimed at the
growing automotive infotainment market. This device
includes two graphics processors, 720p video
processing, dual display, and many I/Os.
The i.MX51A processor features Freescale’s advanced
implementation of the ARM Cortex A8™ core, targeting
speeds up to 600 MHz with 200 MHz I/O bus clock
DDR2 and mobile DDR. This device is well-suited for
graphics rendering for HMI and navigation, high
performance speech processing with large databases,
video processing and display, audio playback and
ripping, and many other applications.
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 2
1.2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1. Special Signal Considerations . . . . . . . . . . . . . . . 11
3. IOMUX Configuration for Boot Media . . . . . . . . . . . . . . . 13
3.1. NAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2. SD/MMC IOMUX Pin Configuration . . . . . . . . . . . 14
3.3. I
2
C IOMUX Pin Configuration . . . . . . . . . . . . . . . . 14
3.4. eCSPI/CSPI IOMUX Pin Configuration . . . . . . . . 15
3.5. Wireless External Interface Module (WEIM) . . . . 15
3.6. UART IOMUX Pin Configuration . . . . . . . . . . . . . 15
3.7. USB-OTG IOMUX Pin Configuration . . . . . . . . . . 15
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1. Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 16
4.2. Supply Power-Up/Power-Down Requirements and
Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4. Output Buffer Impedance Characteristics . . . . . . 29
4.5. I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 33
4.6. Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.7. External Peripheral Interfaces . . . . . . . . . . . . . . . 72
5. Package Information and Contact Assignments . . . . . 151
5.1. 19 x 19 mm Package Information . . . . . . . . . . . . 151
5.2. 19 x 19 mm, 0.8 Pitch Ball Map . . . . . . . . . . . . . 169
6. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
© 2012 Freescale Semiconductor, Inc. All rights reserved.
Introduction
Features of the i.MX51A processor include the following:
• Smart Speed Technology—The i.MX51A device has power management throughout the IC that
enables the rich suite of multimedia feature and peripherals to achieve minimum power
consumption in both active and various low power modes. Smart Speed Technology enables the
designer to deliver a feature-rich product that requires levels of power that are far less than industry
expectations.
• Multimedia—The multimedia performance of the ARM Cortex A8 is enhanced with a multi-level
cache system, a Multi-standard Hardware Video CODECs, autonomous image processing unit,
multi-standard audio CODECs, Neon (an advanced SIMD, 32 bit single-precision floating point
support and vector floating point co-processor), and a programmable smart DMA controller.
• Powerful Graphics Acceleration—The i.MX51A processor has an integrated Graphics Processing
Unit which includes an OpenGl 2.0 GPU that provides 27Mtri/sec, 166Mpix/s, and 664Mpix/s
z-plane performance. Silicon version 2.0 of the i.MX51A device includes an independent OpenVG
GPU operating at166Mpix/s.
• Interface Flexibility—The i.MX51A processor supports connections to all popular types of
external memories: mobile DDR, DDR2, PSRAM, NOR Flash, NAND Flash (MLC and SLC), and
OneNAND (managed NAND). The i.MX51A processor also includes a rich multimedia suite of
interfaces: LCD controller for two displays, CMOS sensor interface, High-Speed USB On-The-Go
plus three High-Speed USB hosts, high-speed MMC/SDIO, Fast Ethernet controller, UART, I2C,
I2S (SSI), and others.
1.1
Ordering Information
Table 1. Ordering Information
Junction
Temperature
Range (
°
C)
–40 to 125
–40 to 125
Package
1
Table 1
provides the ordering information.
Part Number
Mask Set
Features
MCIMX514AJM6C
MCIMX516AJM6C
1
M77X
M77X
No hardware video codecs
Full specification
19 x 19 mm, 0.8 mm pitch BGA
Case 2017
19 x 19 mm, 0.8 mm pitch BGA
Case 2017
Case 2017 and Case 2058 are RoHS compliant, lead-free, MSL = 3.
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
2
Freescale Semiconductor
Introduction
1.2
Block Diagram
TV-Out
Access.
Conn.
Figure 1
shows the functional modules of the processor.
Digital
Audio
DDR
Memory
NOR/Nand Battery Ctrl
Device
Flash
USB
Dev/Host
Camera 1
Camera 2
LCD Display 1
LCD Display 2
ATA HDD
External
Memory I/F
USB PHY
Application Processor Domain (AP)
TV Encoder
USB OTG +
3 HS Ports
Smart DMA
(SDMA)
Ethernet
Image Processing
Subsystem
AP Peripherals
eCSPI
(2
)
CSPI
UART (3)
AUDMUX
SPBA
AXI and AHB Switch Fabric
Internal
RAM
(128 Kbytes)
Boot
ROM
ARM Cortex A8
Platform
ARM Cortex A8
Neon and VFP
I
2
C(2),HSI
2
C
1-WIRE
PWM (2)
IIM
IOMUXC
KPP
GPIOx32 (4)
SJC
SSI (3)
FIRI
Debug
DAP
TPIU
CTI (2)
SDMA Peripherals
eSDHC (4)
UART
SPDIF Tx
FEC
SSI
eCSPI
(1 of 2)
SIM
P-ATA
Freescale Semiconductor
GPS
RF/IF ICs
SIM
Audio/Power
Management
L1 I/D cache
L2 cache
ETM, CTI0,1
Security
SAHARA
Lite
RTIC
SCC
SRTC
CSU
TZIC
Timers
WDOG (2)
GPT
EPIT (2)
Video
Proc. Unit
(VPU)
3D Graphics
Proc Unit
(GPU)
Fuse Box
Graphics
Memory
(128 Kbytes)
2D Graphics
Proc Unit
(GPU2D)
Clock and Reset
PLL (3)
CCM
GPC
SRC
XTALOSC
CAMP (2)
JTAG
IrDA
XVR
Bluetooth
WLAN
USB-OTG
XVR
MMC/SDIO
Keypad
Figure 1. Functional Block Diagram
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
3
Features
2
Features
Table 2. i.MX51A Digital and Analog Modules
The i.MX51A processor contains a large number of digital and analog modules that are described in
Table 2.
Block
Mnemonic
1-WIRE
ARM
Cortex™-A8
Block Name
1-Wire
Interface
ARM
Cortex™-A8
Platform
Subsystem
Connectivity
Peripherals
ARM
Brief Description
1-Wire support provided for interfacing with an on-board EEPROM, and smart
battery interfaces, for example: Dallas DS2502.
The ARM Cortex™-A8 Core Platform consists of the ARM Cortex™-A8
processor version r2p5 (with TrustZone) and its essential sub-blocks. It contains
the Level 2 Cache Controller, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data
cache, and a 256 Kbyte L2 cache. The platform also contains an Event Monitor
and Debug modules. It also has a NEON co-processor with SIMD media
processing architecture, register file with 32
×
64-bit general-purpose registers,
an Integer execute pipeline (ALU, Shift, MAC), dual, single-precision floating
point execute pipeline (FADD, FMUL), load/store and permute pipeline and a
Non-Pipelined Vector Floating Point (VFP) co-processor (VFPv3).
The elements of the audio subsystem are three Synchronous Serial Interfaces
(SSI1-3), a Digital Audio Mux (AUDMUX), and Digital Audio Out (SPDIF TX).
See the specific interface listings in this table.
The AUDMUX is a programmable interconnect for voice, audio, and
synchronous data routing between host serial interfaces (for example, SSI1,
SSI2, and SSI3) and peripheral serial interfaces (audio and voice codecs). The
AUDMUX has seven ports (three internal and four external) with identical
functionality and programming models. A desired connectivity is achieved by
configuring two or more AUDMUX ports.
Audio
Subsystem
AUDMUX
Audio
Subsystem
Digital Audio
Mux
Multimedia
Peripherals
Multimedia
Peripherals
CCM
GPC
SRC
CSPI-1,
eCSPI-2
eCSPI-3
CSU
These modules are responsible for clock and reset distribution in the system,
Clock Control Clocks,
and also for system power management. The modules include three PLLs and
Resets, and
Module
Global Power Power Control a Frequency Pre-Multiplier (FPM).
Controller
System Reset
Controller
Configurable
SPI,
Enhanced
CSPI
Central
Security Unit
Connectivity
Peripherals
Full-duplex enhanced Synchronous Serial Interface, with data rate up to
66.5 Mbit/s (for eCSPI, master mode). It is configurable to support Master/Slave
modes, four chip selects to support multiple peripherals.
The Central Security Unit (CSU) is responsible for setting comprehensive
security policy within the i.MX51 platform, and for sharing security information
between the various security modules. The Security Control Registers (SCR) of
the CSU are set during boot time by the High Assurance Boot (HAB) code and
are locked to prevent further writing.
The Debug System provides real-time trace debug capability of both instructions
and data. It supports a trace protocol that is an integral part of the ARM Real
Time Debug solution (RealView). Real-time tracing is controlled by specifying a
set of triggering and filtering resources, which include address and data
comparators, cross-system triggers, counters, and sequencers.
Security
Debug
System
Debug
System
System
Control
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
4
Freescale Semiconductor
Features
Table 2. i.MX51A Digital and Analog Modules (continued)
Block
Mnemonic
EMI
Block Name
External
Memory
Interface
Subsystem
Connectivity
Peripherals
Brief Description
The EMI is an external and internal memory interface. It performs arbitration
between multi-AXI masters to multi-memory controllers, divided into four major
channels: fast memories (Mobile DDR, DDR2) channel, slow memories
(NOR-FLASH/PSRAM/NAND-FLASH and so on) channel, internal memory
(RAM, ROM) channel and graphical memory (GMEM) Channel.
In order to increase the bandwidth performance, the EMI separates the buffering
and the arbitration between different channels so parallel accesses can occur.
By separating the channels, slow accesses do not interfere with fast accesses.
EMI features:
• 64-bit and 32-bit AXI ports
• Enhanced arbitration scheme for fast channel, including dynamic master
priority, and taking into account which pages are open or closed and what
type (Read or Write) was the last access
• Flexible bank interleaving
• Supports 16/32-bit Mobile DDR up to 200 MHz SDCLK (mDDR400)
• Supports 16/32-bit (Non-Mobile) DDR2 up to 200 MHz SDCLK (DDR2-400)
• Supports up to 2 Gbit Mobile DDR memories
• Supports 16-bit (in muxed mode only) PSRAM memories (sync and async
operating modes), at slow frequency, for debugging purposes
• Supports 32-bit NOR-Flash memories (only in muxed mode), at slow
frequencies for debugging purposes
• Supports 4/8-ECC, page sizes of 512 Bytes, 2 Kbytes and 4 Kbytes
• NAND-Flash (including MLC)
• Multiple chip selects
• Enhanced Mobile DDR memory controller, supporting access latency hiding
• Supports watermarking for security (Internal and external memories)
• Supports Samsung OneNAND
™
(only in muxed I/O mode)
Each EPIT is a 32-bit “set and forget” timer that starts counting after the EPIT is
enabled by software. It is capable of providing precise interrupts at regular
intervals with minimal processor intervention. It has a 12-bit prescaler for division
of input clock frequency to get the required time setting for the interrupts to occur,
and counter values can be programmed on the fly.
The features of the eSDHC module, when serving as host, include the following:
• Conforms to SD Host Controller Standard Specification version 2.0
• Compatible with the MMC System Specification version 4.2
• Compatible with the SD Memory Card Specification version 2.0
• Compatible with the SDIO Card Specification version 1.2
• Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD
Combo, MMC and MMC RS cards
• Configurable to work in one of the following modes:
—SD/SDIO 1-bit, 4-bit
—MMC 1-bit, 4-bit, 8-bit
• Full-/high-speed mode
• Host clock frequency variable between 32 kHz to 52 MHz
• Up to 200 Mbps data transfer for SD/SDIO cards using four parallel data lines
• Up to 416 Mbps data transfer for MMC cards using eight parallel data lines
EPIT-1
EPIT-2
Enhanced
Periodic
Interrupt
Timer
Timer
Peripherals
eSDHC-1
eSDHC-2
eSDHC-3
Connectivity
Enhanced
Peripherals
Multi-Media
Card/
Secure Digital
Host
Controller
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
Freescale Semiconductor
5
京公网安备 11010802033920号
EEWORLD
