87973DYILF datasheet, PDF - EEWORLD Datasheet

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87973DYILF: Categorysemiconductor Analog mixed-signal IC; File Size238KB，17 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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87973DYILF Parametric

Parameter Name	Attribute value
Product Category	Clock Generators & Support Products
Manufacturer	IDT (Integrated Device Technology, Inc.)
RoHS	Details
Type	Clock Generators
Maximum Input Frequency	120 MHz
Max Output Freq	125 MHz
Number of Outputs	14 Output
Operating Supply Voltage	3.3 V
Operating Supply Current	225 mA
Maximum Operating Temperature	+ 85 C
Minimum Operating Temperature	- 40 C
Mounting Style	SMD/SMT
Package / Case	TQFP-52
Packaging	Tray
Height	1.4 mm
Jitter	100 ps
Length	10 mm
Factory Pack Quantity	160
Width	10 mm
Unit Weight	0.009171 oz

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Low Skew, 1-to-12 LVCMOS / LVTTL

Clock Multiplier/Zero Delay Buffer

Data Sheet

87973

ENERAL

ESCRIPTION

The 87973 is a LVCMOS/LVTTL clock generator.

The 87973 has three selectable inputs and provides

fourteen LVCMOS/LVTTL outputs.

The 87973 is a highly ﬂexible device. The three selectable in-

puts (1 differential and 2 single ended inputs) are often used in

systems requiring redundant clock sources. Up to three

different output frequencies can be generated among the three

output banks.

The three output banks and feedback output each have their

own output dividers which allows the device to generate a

multitude of different bank frequency ratios and output-to-input

frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3)

can be selected to be inverting or non-inverting. The output

frequency range is 8.33MHz to125MHz. The input frequency

range is 5MHz to 120MHz.

The 87973 also has a QSYNC output which can by used for

system synchronization purposes. It monitors Bank A and

Bank C outputs and goes low one period prior to coincident

rising edges of Bank A and Bank C clocks. QSYNC then goes

high again when the coincident rising edges of Bank A and

Bank C occur. This feature is used primarily in applications

where Bank A and Bank C are running at different frequencies,

and is particularly useful when they are running at non-integer

multiples of one another.

Example Applications:

System Clock generator:

Use a 16.66MHz reference

clock to generate eight 33.33MHz copies for PCI and

four 100MHz copies for the CPU or PCI-X.

Line Card Multiplier:

Multiply differential 62.5MHz from

a back plane to single-ended 125MHz for the line Card

ASICs and Gigabit Ethernet Serdes.

Zero Delay buffer for Synchronous memory:

Fan out

up to twelve 100MHz copies from a memory controller

reference clock to the memory chips on a memory mod-

ule with zero delay.

EATURES

•

Fully integrated PLL

•

Fourteen LVCMOS/LVTTL outputs; twelve clock outputs,

one feedback, one sync

•

Selectable LVCMOS/LVTTL or differential CLK, nCLK inputs

•

CLK0, CLK1 can accept the following input levels:

LVCMOS or LVTTL

•

CLK, nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

•

Output frequency range: 8.33MHz to 125MHz

•

VCO range: 200MHz to 480MHz

•

Output skew: 550ps (maximum)

•

Cycle-to-cycle jitter: ±100ps (typical)

•

Full 3.3V supply voltage

•

-40°C to 85°C ambient operating temperature

•

Available in lead-free RoHS compliant package

•

Compatible with PowerPC™ and Pentium™ Microprocessors

SSIGNMENT

December 7, 2015

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