ATUC64D4-Z1UR datasheet, PDF - EEWORLD Datasheet

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ATUC64D4-Z1UR: Description32-bit Microcontrollers - MCU UC3D4 64KB FL 85C; Categorysemiconductor The embedded processor and controller; File Size2MB，378 Pages; ManufacturerAtmel (Microchip)

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ATUC64D4-Z1UR Overview

32-bit Microcontrollers - MCU UC3D4 64KB FL 85C

ATUC64D4-Z1UR Parametric

Parameter Name	Attribute value
Product Category	32-bit Microcontrollers - MCU
Manufacturer	Atmel (Microchip)
RoHS	Details
Core	AVR
Data Bus Width	32 bit
Processor Series	ATUC
Packaging	Reel
Product	MCU
Factory Pack Quantity	4000

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Feature Summary

•

32-bit load/store RISC architecture

Up to 15 general-purpose 32-bit registers

32-bit Stack Pointer, Program Counter, and Link Register reside in register file

Fully orthogonal instruction set

Pipelined architecture allows one instruction per clock cycle for most instructions

Byte, half-word, word and double word memory access

Fast interrupts and multiple interrupt priority levels

Optional branch prediction for minimum delay branches

Privileged and unprivileged modes enabling efficient and secure Operating Systems

Innovative instruction set together with variable instruction length ensuring industry

leading code density

Optional DSP extention with saturated arithmetic, and a wide variety of multiply

instructions

Optional extensions for Java, SIMD, Read-Modify-Write to memory, and Coprocessors

Architectural support for efficient On-Chip Debug solutions

Optional MPU or MMU allows for advanced operating systems

FlashVault

™

support through Secure State for executing trusted code alongside

nontrusted code on the same CPU

AVR32

Architecture

Document

32000D–04/2011

1. Introduction

AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for cost-sensitive

embedded applications, with particular emphasis on low power consumption and high code den-

sity. In addition, the instruction set architecture has been tuned to allow for a variety of

microarchitectures, enabling the AVR32 to be implemented as low-, mid- or high-performance

processors. AVR32 extends the AVR family into the world of 32- and 64-bit applications.

1.1

The AVR family

The AVR family was launched by Atmel in 1996 and has had remarkable success in the 8-and

16-bit flash microcontroller market. AVR32 is complements the current AVR microcontrollers.

Through the AVR32 family, the AVR is extended into a new range of higher performance appli-

cations that is currently served by 32- and 64-bit processors

To truly exploit the power of a 32-bit architecture, the new AVR32 architecture is not binary com-

patible with earlier AVR architectures. In order to achieve high code density, the instruction

format is flexible providing both compact instructions with 16 bits length and extended 32-bit

instructions. While the instruction length is only 16 bits for most instructions, powerful 32-bit

instructions are implemented to further increase performance. Compact and extended instruc-

tions can be freely mixed in the instruction stream.

1.2

The AVR32 Microprocessor Architecture

The AVR32 is a new innovative microprocessor architecture. It is a fully synchronous synthesis-

able RTL design with industry standard interfaces, ensuring easy integration into SoC designs

with legacy intellectual property (IP). Through a quantitative approach, a large set of industry

recognized benchmarks has been compiled and analyzed to achieve the best code density in its

class of microprocessor architectures. In addition to lowering the memory requirements, a com-

pact code size also contributes to the core’s low power characteristics. The processor supports

byte and half-word data types without penalty in code size and performance.

Memory load and store operations are provided for byte, half-word, word and double word data

with automatic sign- or zero extension of half-word and byte data. The C-compiler is closely

linked to the architecture and is able to exploit code optimization features, both for size and

speed.

In order to reduce code size to a minimum, some instructions have multiple addressing modes.

As an example, instructions with immediates often have a compact format with a smaller imme-

diate, and an extended format with a larger immediate. In this way, the compiler is able to use

the format giving the smallest code size.

Another feature of the instruction set is that frequently used instructions, like add, have a com-

pact format with two operands as well as an extended format with three operands. The larger

format increases performance, allowing an addition and a data move in the same instruction in a

single cycle.

Load and store instructions have several different formats in order to reduce code size and

speed up execution:

• Load/store to an address specified by a pointer register

• Load/store to an address specified by a pointer register with postincrement

AVR32

32000D–04/2011

AVR32

• Load/store to an address specified by a pointer register with predecrement

• Load/store to an address specified by a pointer register with displacement

• Load/store to an address specified by a small immediate (direct addressing within a small

page)

• Load/store to an address specified by a pointer register and an index register.

The register file is organized as 16 32-bit registers and includes the Program Counter, the Link

function calls and is used implicitly by some instructions.

The AVR32 core defines several micro architectures in order to capture the entire range of appli-

cations. The microarchitectures are named AVR32A, AVR32B and so on. Different

microarchitectures are suited to different end applications, allowing the designer to select a

microarchitecture with the optimum set of parameters for a specific application.

1.2.1

Exceptions and Interrupts

The AVR32 incorporates a powerful exception handling scheme. The different exception

sources, like Illegal Op-code and external interrupt requests, have different priority levels, ensur-

ing a well-defined behavior when multiple exceptions are received simultaneously. Additionally,

pending exceptions of a higher priority class may preempt handling of ongoing exceptions of a

lower priority class. Each priority class has dedicated registers to keep the return address and

status register thereby removing the need to perform time-consuming memory operations to

save this information.

There are four levels of external interrupt requests, all executing in their own context. The con-

texts can provide a number of dedicated registers for the interrupts to use directly ensuring low

latency. High priority interrupts may have a larger number of shadow registers available than low

priority interrupts. An interrupt controller does the priority handling of the external interrupts and

provides the prioritized interrupt vector to the processor core.

1.2.2

Java Support

Java hardware acceleration is available as an option, in the form of a Java Card or Java Virtual

Machine hardware implementation.

1.2.3

FlashVault

Revision 3 of the AVR32 architecture introduced a new CPU state called Secure State. This

state is instrumental in the new security technology named FlashVault. This innovation allows

the on-chip flash and other memories to be partially programmed and locked, creating a safe on-

chip storage for secret code and valuable software intellectual property. Code stored in the

FlashVault will execute as normal, but reading, copying or debugging the code is not possible.

This allows a device with FlashVault code protection to carry a piece of valuable software such

as a math library or an encryption algorithm from a trusted location to a potentially untrustworthy

partner where the rest of the source code can be developed, debugged and programmed.

32000D–04/2011

1.3

Microarchitectures

The AVR32 architecture defines different microarchitectures. This enables implementations that

are tailored to specific needs and applications. The microarchitectures provide different perfor-

mance levels at the expense of area and power consumption. The following microarchitectures

are defined:

1.3.1

AVR32A

The AVR32A microarchitecture is targeted at cost-sensitive, lower-end applications like smaller

microcontrollers. This microarchitecture does not provide dedicated hardware registers for shad-

owing of register file registers in interrupt contexts. Additionally, it does not provide hardware

registers for the return address registers and return status registers. Instead, all this information

is stored on the system stack. This saves chip area at the expense of slower interrupt handling.

Upon interrupt initiation, registers R8-R12 are automatically pushed to the system stack. These

registers are pushed regardless of the priority level of the pending interrupt. The return address

and status register are also automatically pushed to stack. The interrupt handler can therefore

use R8-R12 freely. Upon interrupt completion, the old R8-R12 registers and status register are

restored, and execution continues at the return address stored popped from stack.

The stack is also used to store the status register and return address for exceptions and

scall.

Executing the

rete

rets

instruction at the completion of an exception or system call will pop

this status register and continue execution at the popped return address.

1.3.2

AVR32B

The AVR32B microarchitecture is targeted at applications where interrupt latency is important.

The AVR32B therefore implements dedicated registers to hold the status register and return

address for interrupts, exceptions and supervisor calls. This information does not need to be

written to the stack, and latency is therefore reduced. Additionally, AVR32B allows hardware

shadowing of the registers in the register file. The INT0 to INT3 contexts may have dedicated

versions of the registers in the register file, allowing the interrupt routine to start executing

immediately.

The

scall, rete

and

rets

instructions use the dedicated status register and return address regis-

ters in their operation. No stack accesses are performed.

AVR32

32000D–04/2011

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