FemtoClock
®
Crystal-to-3.3V
LVPECL Frequency Synthesizer
G
ENERAL
D
ESCRIPTION
The 843003i-01 is a 3 differential output LVPECL Synthesizer
designed to generate Ethernet reference clock frequencies. Using
a 19.53125MHz or 25MHz, 18pF parallel resonant crystal, the
following frequencies can be generated based on the settings
of 4 frequency select pins (DIV_SEL[A1:A0], DIV_SEL[B1:B0]):
625MHz, 312.5MHz, 156.25MHz, and 125MHz. The 843003I-01
has 2 output banks, Bank A with 1 differential LVPECL output pair
and Bank B with 2 differential LVPECL output pairs.
The two banks have their own dedicated frequency select pins and
can be independently set for the frequencies mentioned above.
The 843003i-01 uses ICS’ 3rd generation low phase noise VCO
technology and can achieve 1ps or lower typical rms phase jitter,
easily meeting Ethernet jitter requirements. The 843003i-01 is
packaged in a small 24-pin TSSOP package.
843003I-01
DATASHEET
F
EATURES
• Three 3.3V LVPECL outputs on two banks, A Bank with one
LVPECL pair and B Bank with two LVPECL output pairs
• Using a 19.53125MHz or 25MHz crystal, the two output banks
can be independently set for 625MHz, 312.5MHz, 156.25MHz
or 125MHz
• Selectable crystal oscillator interface or LVCMOS/LVTTL sin-
gle-ended input
• VCO range: 490MHz to 680MHz
• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):
0.53ps (typical)
• 3.3V output supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free RoHS compliant package
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
DIV_SELB0
VCO_SEL
MR
V
CCO
_
A
QA0
nQA0
OEB
OEA
FB_DIV
V
CCA
V
CC
DIV_SELA0
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DIV_SELB1
V
CCO
_
B
QB0
nQB0
QB1
nQB1
XTAL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
V
EE
DIV_SELA1
843003I-01
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
843003I-01 REVISION A DECEMBER 8, 2014
1
©2014 Integrated Device Technology, Inc.
843003I-01 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
24
2
Name
DIV_SELB0
DIV_SELB1
VCO_SEL
Input
Type
Pullup
Description
Input
3
MR
Input
Division select pin for Bank B. Default = HIGH.
LVCMOS/LVTTL interface levels.
VCO select pin. When Low, the PLL is bypassed and the crystal reference or
REF_CLK (depending on XTAL_SEL setting) are passed directly to the output
Pullup
dividers. Has an internal pullup resistor so the PLL is not bypassed by default.
LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx
Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled.
Has an internal pulldown resistor so the power-up default state of outputs and
dividers are enabled. LVCMOS/LVTTL interface levels.
Output supply pin for Bank A outputs.
Differential output pair. LVPECL interface levels.
Output enable Bank B. Active High output enable. When logic HIGH, the 2
output pairs on Bank B are enabled. When logic LOW, the output pairs drive
differential Low (QB0=Low, nQB0=High). Has an internal pullup resistor so the
default power-up state of outputs are enabled.
LVCMOS/LVTTL interface levels.
Output enable Bank A. Active High output enable. When logic HIGH, the
output pair on Bank A is enabled. When logic LOW, the output pair drives
differential Low (QA0=Low, nQA0=High). Has an internal pullup resistor so the
default power-up state of outputs are enabled. LVCMOS/LVTTL interface levels.
Feedback divide select. When Low (default), the feedback divider is set for ÷25.
When HIGH, the feedback divider is set for ÷32.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Core supply pin.
Pullup
Division select pin for Bank A. Default = HIGH.
LVCMOS/LVTTL interface levels.
Negative supply pin.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the in-
put. XTAL_IN is also the overdrive pin if you want to overdrive the crystal circuit
with a single-ended reference clock.
Single-ended reference clock input. Has an internal pulldown resistor to pull to
Pulldown low state by default. Can leave floating if using the crystal interface. LVCMOS/
LVTTL interface levels.
Crystal select pin. Selects between the single-ended REF_CLK or crystal
Pullup interface. Has an internal pullup resistor so the crystal interface is selected by
default. LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Output supply pin for Bank B outputs.
4
5, 6
V
CCO_A
QA0, nQA0
Power
Ouput
7
OEB
Input
Pullup
8
OEA
Input
Pullup
9
10
11
12
13
14
15, 16
FB_DIV
V
CCA
V
CC
DIV_SELA0
DIV_SELA1
V
EE
XTAL_OUT,
XTAL_IN
REF_CLK
Input
Power
Power
Input
Power
Input
Pulldown
17
Input
18
19, 20
21, 22
23
Pullup and Pulldown
XTAL_SEL
nQB1, QB1
nQB0, QB0
V
CCO_B
Input
Output
Output
Power
NOTE: refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
FemtoClock
®
Crystal-to-3.3V LVPECL Frequency Synthesizer
2
REVISION A 12/8/14
843003I-01 DATA SHEET
T
ABLE
3A. B
ANK
A F
REQUENCY
T
ABLE
Inputs
Crystal Frequency
(MHz)
25
25
20
22.5
25
24
20
19.44
19.44
15.625
18.75
19.44
18.75
15.625
FB_DIV
0
0
0
0
0
0
0
1
1
1
1
1
1
1
DIV_SELA1
0
0
0
1
1
1
1
0
0
0
1
1
1
1
DIV_SELA0
0
1
1
0
1
1
1
0
1
1
0
1
1
1
Feedback
Divider
25
25
25
25
25
25
25
32
32
32
32
32
32
32
Bank A
Output Divider
1
2
2
3
4
4
4
1
2
2
3
4
4
4
M/N
QA0/nQA0
Multiplication Output Fre-
Factor
quency (MHz)
25
12.5
12.500
8.333
6.25
6.25
6.25
32
16
16
10.667
8
8
8
625
312.5
250
187.5
156.25
150
125
622.08
311.04
250
200
155.52
150
125
T
ABLE
3B. B
ANK
B F
REQUENCY
T
ABLE
Inputs
Crystal Frequency
(MHz)
25
20
25
24
20
25
25
24
20
19.44
15.625
19.44
18.75
15.625
15.625
19.44
18.75
15.625
FB_DIV
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
DIV_SELB1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
DIV_SELB0
0
0
1
1
1
0
1
1
1
0
0
1
1
1
0
1
1
1
Feedback
Divider
25
25
25
25
25
25
25
25
25
32
32
32
32
32
32
32
32
32
Bank B
Output Divider
2
2
4
4
4
5
8
8
8
2
2
4
4
4
5
8
8
8
M/N
Multiplication
Factor
12.5
12.5
6.25
6.25
6.25
5
3.125
3.125
3.125
16
16
8
8
8
6.4
4
4
4
QBx/nQBx
Output Fre-
quency
(MHz)
312.5
250
156.25
150
125
125
78.125
75
62.5
311.04
250
155.52
150
125
100
77.76
75
62.5
FemtoClock
®
Crystal-to-3.3V LVPECL Frequency Synthesizer
3
REVISION A 12/8/14
843003I-01 DATA SHEET
T
ABLE
3C. O
UTPUT
B
ANK
A C
ONFIGURATION
S
ELECT
F
UNCTION
T
ABLE
Inputs
DIV_SELA1
0
0
1
1
DIV_SELA0
0
1
0
1
Outputs
QA
÷1
÷2
÷3
÷4
T
ABLE
3D. O
UTPUT
B
ANK
B C
ONFIGURATION
S
ELECT
F
UNCTION
T
ABLE
Inputs
DIV_SELB1
0
0
1
1
DIV_SELB0
0
1
0
1
Outputs
QBx
÷2
÷4
÷5
÷8
T
ABLE
3E. F
EEDBACK
D
IVIDER
C
ONFIGURATION
S
ELECT
F
UNCTION
T
ABLE
Inputs
FB_DIV
0
1
Feedback Divide
÷25
÷32
T
ABLE
3F. OEA S
ELECT
F
UNCTION
T
ABLE
Inputs
OEA
0
1
QA0
LOW
Active
Outputs
nQA0
HIGH
Active
T
ABLE
3G. OEB S
ELECT
F
UNCTION
T
ABLE
Inputs
OEB
0
1
LOW
Active
Outputs
QB0:QB1
nQB0:nQB1
HIGH
Active
REVISION A 12/8/14
4
FemtoClock
®
Crystal-to-3.3V LVPECL Frequency Synthesizer
843003I-01 DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
70°C/W (0 lfpm)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_A
= V
CCO_B
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO_A, B
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
CC
– 0.20
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
CC
3.465
150
20
Units
V
V
V
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_A
= V
CCO_B
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input Low Voltage
REF_CLK, MR, FB_DIV
I
IH
Input
High Current
DIV_SELA0, DIV_SELA1,
DIV_SELB0, DIV_SELB1,
VCO_SEL, XTAL_SEL,
OEA, OEB
REF_CLK, MR, FB_DIV
I
IL
Input
Low Current
DIV_SELA0, DIV_SELA1,
DIV_SELB0, DIV_SELB1,
VCO_SEL, XTAL_SEL,
OEA, OEB
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_A
= V
CCO_B
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Ω
CCO_A/B
Test Conditions
Minimum
V - 1.4
CCO_A/B
Typical
Maximum
V- 0.9
CCO_A/B
Units
V
V
V
V - 2.0
CCO_A/B
V - 1.7
CCO_A/B
0.6
1.0
NOTE 1: Outputs terminated with 50 to V - 2V.
FemtoClock
®
Crystal-to-3.3V LVPECL Frequency Synthesizer
5
REVISION A 12/8/14
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