ST16C450
UNIVERSAL ASYNCHRONOUS
RECEIVER/TRANSMITTER (UART)
September 2003
GENERAL DESCRIPTION
The ST16C450 is a universal asynchronous receiver
and transmitter. The ST16C450 is an improved ver-
sion of the NS16450 UART with higher operating
speed and lower access time. A programmable baud
rate generator is provided to select transmit and
receive clock rates from 50 Bps to 1.5 Mbps.
The ST16C450 on board status registers provides the
error conditions, type and status of the transfer
operation being performed. Included is complete
MODEM control capability, and a processor interrupt
system that may be software tailored to the user’s
requirements. The ST16C450 provides internal loop-
back capability for on board diagnostic testing.
The ST16C450 is available in 40 pin PDIP, 44 pin
PLCC, and 48 pin TQFP packages. It is fabricated in
an advanced CMOS process to achieve low drain
power and high speed requirements.
PLCC Package
-DSR
41
-CTS
40
39
38
37
36
35
VCC
N.C.
-CD
42
-RI
43
D4
D3
D2
D1
D0
D5
D6
D7
RCLK
RX
N.C.
TX
CS0
CS1
-CS2
-BAUDOUT
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
44
6
5
4
3
2
1
RESET
-OP1
-DTR
-RTS
-OP2
N.C.
INT
N.C.
A0
A1
A2
ST16C450CJ44
34
33
32
31
30
29
XTAL1
XTAL2
-IOW
-IOR
-DDIS
IOW
N.C.
FEATURES
•
Pin to pin and functionally compatible to the Indus-
try Standard 16450
•
2.97 to 5.5 volt operation
•
1.5 Mbps transmit/receive operation (24MHz)
•
Programmable word lengths (5, 6, 7, 8)
•
Even, odd, force, or no parity generation and
detection
•
Independent transmit and receive control
•
Standard modem interface
•
Low operating current ( 1.2mA typ.)
ORDERING INFORMATION
Part number
Package
Operating temperature
Device Status
ST16C450CP40
ST16C450CJ44
ST16C450CQ48
ST16C450IP40
ST16C450IJ44
ST16C450IQ48
40-Lead
44-Lead
48-Lead
40-Lead
44-Lead
48-Lead
PDIP
PLCC
TQFP
PDIP
PLCC
TQFP
0° C to + 70° C
0° C to + 70° C
0° C to + 70° C
-40° C to + 85° C
-40° C to + 85° C
-40° C to + 85° C
Active. See the ST16C450CQ48 for new designs.
Active
Active
Active. See the ST16C450IQ48 for new designs.
Active
Active
Rev. 4.20
EXAR
Corporation, 48720 Kato Road, Fremont, CA 94538
•
(510) 668-7000
•
FAX (510) 668-7017
CSOUT
GND
IOR
-AS
ST16C450
Figure 1, PACKAGE DESCRIPTION, ST16C450
48 Pin TQFP Package
40 Pin DIP Package
-DSR
-CTS
VCC
N.C.
N.C.
-CD
-RI
D4
D3
D2
D1
D0
D0
D1
D2
1
2
3
4
5
6
7
40
39
38
37
36
35
34
VCC
-RI
-CD
-DSR
-CTS
RESET
-OP1
-DTR
-RTS
-OP2
INT
N.C.
A0
A1
A2
-AS
CSOUT
-DDIS
IOR
-IOR
48
47
46
45
44
43
42
41
40
39
38
37
N.C.
D5
D6
D7
RCLK
N.C.
RX
TX
CS0
CS1
-CS2
-BAUDOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
N.C.
RESET
D3
D4
-OP1
-DTR
-RTS
-OP2
INT
N.C.
A0
A1
A2
N.C.
D5
D6
D7
RCLK
RX
TX
CS0
CS1
-CS2
-BAUDOUT
XTAL1
XTAL2
-IOW
IOW
GND
ST16C450CQ48
31
30
29
28
27
26
25
8
9
10
11
12
13
14
15
16
17
18
19
20
ST16C450CP40
33
32
31
30
29
28
27
26
25
24
23
22
21
XTAL1
XTAL2
-DDIS
IOW
IOR
Rev. 4.20
2
CSOUT
-IOW
GND
-IOR
N.C.
N.C.
-AS
ST16C450
Figure 2, BLOCK DIAGRAM
D0-D7
-IOR,IOR
-IOW,IOW
RESET
Data bus
&
Control Logic
Transmit
Shift
Register
TX
Inter Connect Bus Lines
&
Control signals
Receive
Shift
Register
RX
A0-A2
-AS
CS0,CS1
-CS2
-DDIS
CSOUT
Register
Select
Logic
-DTR,-RTS
-OP1,-OP2
Clock
&
Baud Rate
Generator
Interrupt
Control
Logic
Modem
Control
Logic
-CTS
-RI
-CD
-DSR
INT
Rev. 4.20
3
XTAL1
RCLK
XTAL2
-BAUDOUT
ST16C450
SYMBOL DESCRIPTION
Symbol
40
A0
A1
A2
IOR
28
27
26
22
Pin
44
31
30
29
25
48
28
27
26
20
Signal
type
I
I
I
I
Pin Description
Address-0 Select Bit Internal registers address selection.
Address-1 Select Bit Internal registers address selection.
Address-2 Select Bit Internal registers address selection.
Read data strobe. Its function is the same as -IOR (see -
IOR), except it is active high. Either an active -IOR or IOR
is required to transfer data from 16C450 to CPU during a
read operation.
Chip Select-0. Logical 1 on this pin provides the chip select-
0 function.
Chip Select-1. Logical 1 on this pin provides the chip select-
1 function.
Chip Select -2. Logical 0 on this pin provides the chip select-
2 function.
Write data strobe. Its function is the same as -IOW (see -
IOW), but it acts as an active high input signal. Either -IOW
or IOW is required to transfer data from the CPU to
ST16C450 during a write operation.
Address Strobe. A logic 0 transition on -AS latches the state
of the chip selects and the register select bits, A0-A2. This
input is used when address and chip selects are not stable
for the duration of a read or write operation, i.e., a micropro-
cessor that needs to de-multiplex the address and data bits.
If not required, the -AS input can be permanently tied to a
logic 0 (it is edge triggered).
CS0
12
14
9
I
CS1
13
15
10
I
-CS2
14
16
11
I
IOW
19
21
17
I
-AS
25
28
24
I
D0-D7
1-8
2-9
43-47
2-4
I/O
Data Bus (Bi-directional) - These pins are the eight bit, tri-
state data bus for transferring information to or from the
controlling CPU. D0 is the least significant bit and the first
data bit in a transmit or receive serial data stream.
Signal and Power Ground.
GND
20
22
18
Pwr
Rev. 4.20
4
ST16C450
SYMBOL DESCRIPTION
Symbol
40
-IOR
21
Pin
44
24
48
19
Signal
type
I
Pin Description
Read data strobe (active low strobe). A logic 0 on this pin
transfers the contents of the ST16C450 data bus to the
CPU.
Write data strobe (active low strobe). A logic 0 on this pin
transfers the contents of the CPU data bus to the addressed
internal register.
Interrupt Request (active high). Interrupts are enabled in the
interrupt enable register (IER), and when an interrupt con-
dition exists. Interrupt conditions include: receiver errors,
available receiver buffer data, transmit buffer empty, or
when a modem status flag is detected.
Chip select out. A high on this pin indicates that the
ST16C450 has been enabled by the chip select pin.
Baud Rate Generator Output. This pin provides the 16X
clock of the selected data rate from the baud rate generator.
The RCLK pin must be connected externally to -BAUDOUT
when the receiver is operating at the same data rate.
Drive Disable. This pin goes to a logic 0 when the external
CPU is reading data from the ST16C450. This signal can be
used to disable external transceivers or other logic func-
tions.
Output-1 (User Defined) - See bit-2 of modem control
register (MCR bit-2).
Reset. (active high) - A logic 1 on this pin will reset the
internal registers and all the outputs. The UART transmitter
output and the receiver input will be disabled during reset
time. (See ST16C450 External Reset Conditions for initial-
ization details.)
Receive Clock Input. This pin is used as external 16X clock
input to the receiver section. External connection to -
Baudout pin is required in order to utilize the internal baud
rate generator.
-IOW
18
20
16
I
INT
30
33
30
O
CSOUT
24
27
23
O
-BAUDOUT
15
17
12
O
-DDIS
23
26
22
O
-OP1
34
38
34
O
RESET
35
39
35
I
RCLK
9
10
5
I
Rev. 4.20
5
京公网安备 11010802033920号
EEWORLD
