Regulators ICs for Digital Cameras and Camcorders
System Switching Regulator ICs
with Built-in FET (10V)
BD9739KN, BD9740KN
●Description
The 7-channel switching regulators include built-in FETs, and are designed for use in digital still cameras.
They feature built-in power FETs and soft start functionality, reducing the number of external components.
●Features
1) Wide supply voltage range: 1.5 V to 10 V
2) High-precision reference voltage: ± 1%
3) Built-in shutdown circuit for overload (timer-latch type)
4) Oscillator frequency is user-adjustable
5) Built-in thermal shutdown circuit
6) Standby mode current: 0
μA
7) Built-in load switch circuit
8) Selectable step-up/step-down mode
9) Supports inverting circuit for negative output voltage
10) Support a constant-current LED drive for backlight applications
11) Includes multiple synchronous rectification channels
●Applications
Digital still cameras, portable DVD players, and digital video cameras.
●Product
lineup
Parameter
Input voltage
Reference voltage precision
Operating frequency range
Step-up
Step-down
Step-up/step-down switch regulator
Inverting
Built-in FET
Synchronous rectification
Load switching
Operating temperature range
Package
BD9739KN
1.5 V to 10 V
1 V ± 1%
100 k to 1.2 MHz
3CH
2CH
1CH
1CH
3CH
3CH
3CH
-20℃ to +85℃
UQFN64
BD9740KN
1.5 V to 10 V
1 V ± 1%
100 k to 1.2 MHz
2CH
1CH
3CH
1CH
1CH
2CH
—
-20℃ to +85℃
UQFN48
No.10036EAT07
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© 2010 ROHM Co., Ltd. All rights reserved.
1/14
2010.09 - Rev.A
BD9739KN,BD9740KN
●Absolute
maximum ratings
Parameter
Symbol
VBAT,VCC,PVCC
PVCCH,PVCCL
DRAIN*H, DRAIN*L
Maximum supply voltage
OUT1B
OUT2B
SWOUT1,4,PGIN1,PG2,3
SWIN*
Power dissipation
Operating temperature range
Storage temperature range
Junction temperature
*1:
*2:
Technical Note
Ratings
BD9739KN
-0.3 to +12
-0.3 to +15
-0.3 to +12
-0.3 to +20
-0.3 to +17
-0.3 to +12
-0.3 to +20
UQFN64
550
*1-2
*2-2
BD9740KN
-0.3 to +12
-0.3 to +15
-0.3 to +12
-0.3 to +20
―
―
―
UQFN48
500
*1-3
760
*2-3
Unit
V
V
V
V
V
V
V
mW
℃
℃
℃
Pd
Topr
Tstg
T
jmax
1000
-25½+85
-55½+125
+125
IC without heat sink operation. Reduce by 5.5 mW/℃ (1-2), or 5.0 mW/℃ (1-3) when Ta
≥
25℃.
When mounted on a PCB (70 mm
70
mm
1.6
mm (thickness), glass epoxy).
Reduced by 10.0 mW/℃ (2-2), or 7.6 mW/℃ (2-3), when Ta
≥
25℃.
●Recommended
operating ranges
Parameter
Symbol
VBAT
Supply voltage
VCC, PVCC
PVCCL, PVCCH
Ratings
Min.
0.1
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
1.2
10
700
300
40
30
200
500
10
100
1
50
50
50
Ratings
BD9739KN
1.5 to 10
1.5 to 10
4.0 to 14
BD9740KN
1.5 to 10
2.8 to 10
4.0 to 14
Unit
V
V
V
Parameter
[Oscillator]
Oscillating frequency
[Driver block]
DRAIN pin input voltage
N-channel FET output current
(step-down)
N-channel FET output current
(step-up)
LED channel output current
Driver output current
Driver peak current
Startup NPN TR sink current
[Positive/negative regulators]
SWOUT1 pin sink current
PGOUT1 pin source current
PG23 pin sink current
SWOUT4 pin source current
SWOUT6 pin source current
SWOUT7 pin source current
Symbol
Unit
Conditions
f
OSC
V
DRAIN
I
OFET1
I
OFET2
I
OLED
I
OUT
I
PEAK
I
NPNSINK
I
SWOUT1
I
PGOUT1
I
PG23
I
SWOUT4
I
SWOUT6
I
SWOUT7
MHz
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
(BD9739KN)
External FET drive circuit
External FET drive circuit
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© 2010 ROHM Co., Ltd. All rights reserved.
2/14
2010.09 - Rev.A
BD9739KN,BD9740KN
Technical Note
●Electrical
characteristics
(Unless otherwise specified, Ta = 25℃, VBAT = 3 V, VCC = 5 V, RT = 11 k, CT = 180 pF, STB1 to STB7 = 3 V)
Limits
Parameter
Symbol
Unit
Conditions
Min.
Typ.
Max.
[Reference voltage, reference voltage for inverting]
Output voltage
V
REF2
0.99
1.0
1.01
V
Line regulation
DV
LI
－
4.0
12.5
mV VCC = 3.0 V to 9.5 V
Load regulation
DV
LO
－
1.0
7.5
mV IREF = 10
μA
to 100
μA
Output current when shorted
I
OS
0.2
1
－
mA VREF = 0 V
[Internal regulator]
Output voltage REGA
V
REGA
2.4
2.5
2.6
V
IREG = 1 mA
[Under voltage lockout circuit]
Detection threshold voltage 1
V
STD1
3.45
3.6
3.75
V
PVCCL monitor
Hysteresis width 1
ΔV
ST1
－
300
－
mV
Detection threshold voltage 2
V
STD2
2.3
2.4
2.5
V
VCC monitor
Hysteresis width 2
ΔV
ST2
－
200
－
mV
Detection threshold voltage 3
V
STD3
－
2.0
－
V
VREGA monitor
Hysteresis width 3
ΔV
ST3
－
50
－
mV
[Startup circuit block]
Oscillating frequency
f
START
50
120
220
kHz
Operation start VBAT voltage
V
ST1
1.5
－
－
V
VBAT pin monitor
Soft start charge current
I
SS1
1.1
2.2
3.3
µA VSS1 = 0 V
[Short protection circuit ]
Timer threshold voltage
V
TC
2.1
2.2
2.3
V
FB pin monitor
0.5
1.0
1.5
VSCP = 0.1 V
SCP pin source current
I
SCP
µA
2
4
6
(BD9740KN)
0.45
0.50
0.55
SCP pin detection voltage
V
TSC
V
0.9
1.0
1.1
(BD9740KN)
SCP pin standby voltage
V
SSC
－
22
170
mV
[Triangular waveform oscillator]
Oscillating frequency
f
OSC1
450
500
550
kHz RT = 11 k, CT = 180 pF
Frequency stability
Df
－
0.3
2
%
VCC = 3.0 V to 9.5 V
RT pin voltage
V
RT
0.78
1.00
1.22
V
[Soft start 23 block] (BD9738KN, BD9739KN)
Soft start charge current
I
SS23
5
10
15
µA VSS23 = 0 V
[Error amp]
Low-level output voltage
V
OL
－
1.3
－
V
INV = 2 V
High-level output voltage
V
OH
V
REGA
- 0.3
－
－
V
INV = 0 V
Output sink current
I
OI
36
72
－
µA FB = 1.7 V, VINV = 1.1 V
Output source current
I
OO
36
72
－
µA FB = 1.7 V, VINV = 0.9 V
DTC pin upper resistance
R
DTCU
20
30
40
kΩ (BD9740KN)
DTC pin lower resistance
R
DTCD
65
95
125
kΩ (BD9740KN)
NON pin input range
I
RES
-0.3
-
1.5
V
Non-inverted pin reference voltage V
NON7
－
0.2
－
V
[PWM comparator]
V
T0
－
1.49
－
V
0% duty
Input threshold voltage
V
T100
－
1.95
－
V
100% duty
MAX DUTY
D
MAX1
77
85
93
%
VINV = 0.9 V, VSCP = 0 V
VINV = 0.9 V,
MAX DUTY (step-up operation)
D
MAX2
77
85
93
%
VSCP, UDSEL = 0 V
[Output circuit]
High-level output voltage
V
SATH
V
CC
-1.6
V
CC
-0.8
－
V
IO = 30 mA
Low-level output voltage
V
SATL
－
0.8
1.6
V
IO = -30 mA
－
270
500
PVCCH = 5 V(IO = 200 mA)
High-side N-channel FET
R
ONH
mΩ
on resistance
－
300
500
(BD9740KN)
－
270
500
PVCCL = 5 V(IO = 200 mA)
Low-side N-channel FET
mΩ
R
ONL
on resistance
－
300
500
(BD9740KN)
CH7 N-channel FET on
－
0.7
1.4
Ω
PVCCL = 5 V(IO = 50 mA)
R
ONL7
resistance
[Step-up/step-down selector ]
Step-down V
UDDO
V
CC
×0.7
－
V
CC
V
UDSEL pin
control voltage
Step-up
V
UDUP
0
－
V
CC
×0.3
V
Note: This IC is not designed to be radiation-resistant.
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© 2010 ROHM Co., Ltd. All rights reserved.
3/14
2010.09 - Rev.A
BD9739KN,BD9740KN
Technical Note
(Unless otherwise specified, Ta = 25℃, VBAT = 3 V, VCC = 5 V, RT = 11 kΩ, CT = 180 pF, STB1 to STB7 = 3 V)
Limits
Parameter
Symbol
Unit
Conditions
Min.
Typ.
Max.
[Power on switching block] (BD9739KN)
Output voltage
V
SAT
－
0.1
0.3
V
IO = 1 mA
SWOUT1
Leak current
I
LEAK
－
0
5
µA STB = 0 V
Output voltage
V
SAT
－
0.1
0.3
V
IO = 100
μA
SWOUT4
Leak current
I
LEAK
－
0
5
µA STB = 0 V
IO = 20 mA
－
V
Output voltage
V
SAT
V
SWIN6
- 0.3 V
SWIN6
- 0.1
VSWIN = 5 V
SWOUT4,6
Leak current
I
LEAK
－
0
5
µA STB = 0 V
IO = 10 mA
Output voltage
V
SAT
V
SWIN7
- 0.3 V
SWIN7
- 0.1
－
V
VSWIN = 10 V
SWOUT7
Leak current
I
LEAK
－
0
5
µA STB = 0 V
[Soft start block] (BD9740KN)
VCC = PVCC = 5V,
mse
PVCCH = 5.0V
Soft start time of CH4
T
SS1
1.8
3.6
6.0
c
STB 0→3 V
Soft start time of CH2, 3
CH2, CH3 soft start
INV4 threshold voltage at start
[STB1 to STB7]
ON
STB pin control voltage
OFF
STB pin pull-down resistance
[Circuit current]
Standby current 1
(VBAT pin sink current)
Standby current 2
(VCC, PVCC pin sink current)
Circuit current at startup
(VBAT pin sink current)
Circuit current 1
(VBAT pin sink current)
Circuit current 2
(VCC, PVCC pin sink current)
T
SS2
V
PG4
V
STBH
V
STBL
R
STB
I
STB1
I
STB2
I
ST
I
CC1
I
CC2
1.8
0.72
2.0
-0.3
250
－
－
－
－
－
3.6
0.80
－
－
400
－
－
30
100
5
6.0
0.88
11
0.3
700
5
5
100
300
15
mse
c
V
V
V
kΩ
µA
µA
mA
µA
mA
VCC = PVCC = 5V,
STB = 3 V
INV4 = 0→1.2 V
VCC = PVCC = 5 V
PVCCH = 5.0 V
STB
STB
STB1 to STB7 = 0 V
STB1 to STB7 = 0 V
CT = 1.7 V
VCC = 0 V
CT = 1.7 V
CT = 1.7 V
INV = 2.5 V
Note: This IC is not designed to be radiation-resistant.
●PVCCH
and PVCCL input voltages
PVCCH
PVCCL
DRAINH
Synchronous rectification channels with built-in FETs include, N-channel FETs
for both the high-side and low-side configuration. The driver block's power
source is supplied to the PVCCL pin for the low-side and the PVCCH pin for
the high-side. (For the BD9740KN, both sides are supplied to the PVCCH pin.)
In order to turn the FET on, a potential of at least 4 V must be supplied to the
PVCCL pin, and a potential of at least, DRAINH pin voltage + 4 V, must be
supplied to the PVCCH pin.
Note:
The breakdown voltage for the PVCCL and PVCCH pins is 15 V.
For applications that with voltages exceeding 15 V, add a zener diode, or other
components, to provide overvoltage protection.
Shorting the DRAINH pin with the ground, while a charge remains in the output
capacitor, may cause unexpected current flow, resulting in damage to the IC.
Add an external protective diode for applications where this possibility exists.
DRAINL
Vo
PGND
Fig. 1 Synchronous Rectification
Channel with Built-In FET
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4/14
2010.09 - Rev.A
BD9739KN,BD9740KN
●Block
diagram and application circuit (BD9739KN)
Connect a capacitor to prevent
oscillation to the VREF pin.
(See page 7.)
For more information
about setting the SCP pin,
(See page 7.)
Connect a capacitor to prevent
oscillation to the VREGA pin.
(See page 7.)
Technical Note
Connect a
capacitor for setting
the soft start time.
(See pages 8& 9.)
Apply the PVCCH pin voltage
with an external charge
pump. (See page 4.)
Connect a
capacitor for soft
start at DTC pin.
(See page 8.)
Connect a resistor for
setting the output voltage.
(See page 8.)
The soft start times for CH4,
6, 7 are fixed internally.
(See page 9.)
Set the operating
frequency with the
RT and CT pins.
(See page 8.)
This pin is used as the
on/off control pin.
(See page 7.)
Set whether CH1 and CH5
will be used as step-up,
step-down or inversion.
(See page 7.)
Fig. 2 BD9739KN Application Circuit
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5/14
2010.09 - Rev.A
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