M1A3P1000-2FG256 datasheet, PDF

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M1A3P1000-2FG256: DescriptionFPGA - Field Programmable Gate Array ProASIC3; CategoryProgrammable logic devices Programmable logic; File Size10MB，210 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

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M1A3P1000-2FG256 Overview

FPGA - Field Programmable Gate Array ProASIC3

M1A3P1000-2FG256 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	BGA,
Reach Compliance Code	compliant
maximum clock frequency	350 MHz
JESD-30 code	S-PBGA-B256
length	17 mm
Humidity sensitivity level	3
Configurable number of logic blocks	24576
Equivalent number of gates	1000000
Number of terminals	256
Maximum operating temperature	85 °C
Minimum operating temperature
organize	24576 CLBS, 1000000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	225
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	1.8 mm
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD/TIN LEAD SILVER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	17 mm
Base Number Matches	1

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Revision 3

Military ProASIC3/EL Low Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

Military Temperature Tested and Qualified

• Each Device Tested from –55°C to 125°C

• Architecture Supports Ultra-High Utilization

Advanced and Pro (Professional) I/Os

††

•

700 Mbps DDR, LVDS-Capable I/Os

1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

†

Bank-Selectable I/O Voltages—up to 8 Banks per Chip

Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and

LVCMOS 2.5 V / 5.0 V Input

†

Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS

Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL

2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3

Class I and II (A3PE3000L only)

I/O Registers on Input, Output, and Enable Paths

Hot-Swappable and Cold-Sparing I/Os

Programmable Output Slew Rate and Drive Strength

Programmable Input Delay (A3PE3000L only)

Schmitt Trigger Option on Single-Ended Inputs (A3PE3000L)

Weak Pull-Up/-Down

IEEE 1149.1 (JTAG) Boundary Scan Test

Pin-Compatible Packages across the Military ProASIC

3EL Family

Firm-Error Immune

• Not Susceptible to Neutron-Induced Configuration Loss

Low Power

• Dramatic Reduction in Dynamic and Static Power

• 1.2 V to 1.5 V Core and I/O Voltage Support for Low Power

†

• Low Power Consumption in Flash*Freeze Mode Allows for

Instantaneous Entry To / Exit From Low-Power Flash*Freeze

Mode

• Supports Single-Voltage System Operation

• Low-Impedance Switches

High Capacity

• 250K to 3M System Gates

• Up to 504 kbits of True Dual-Port SRAM

• Up to 620 User I/Os

Reprogrammable Flash Technology

•

130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

Live-at-Power-Up (LAPU) Level 0 Support

Single-Chip Solution

Retains Programmed Design when Powered Off

Clock Conditioning Circuit (CCC) and PLL

• Six CCC Blocks—One Block with Integrated PLL in ProASIC3

and All Blocks with Integrated PLL in ProASIC3EL

• Configurable Phase Shift, Multiply/Divide, Delay Capabilities,

and External Feedback

• Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V

systems) and 350 MHz (1.5 V systems)

High Performance

• 350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System

Performance

• 3.3 V, 66 MHz, 64-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit

PCI (1.2 V systems)

SRAMs and FIFOs

• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,

and ×18 organizations available)

• True Dual-Port SRAM (except ×18)

• 24 SRAM and FIFO Configurations with Synchronous

Operation:

– 250 MHz: For 1.2 V Systems

– 350 MHz: For 1.5 V Systems

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

• FlashLock

to Secure FPGA Contents

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

• High-Performance, Low-Skew Global Network

Table 1 •

Military ProASIC3/EL Low-Power Devices

A3P250

ARM

Processor Support in ProASIC3/EL FPGAs

• ARM Cortex™-M1 Soft Processor Available with or without

Debug

A3PE600L

A3P1000

M1A3P1000

24,576

144

Yes

154

A3PE3000L

M1A3PE3000L

75,264

504

112

Yes

620

ProASIC3/EL Devices

Devices

ARM Cortex-M1

System Gates

250,000

600,000

VersaTiles (D-flip-flops)

6,144

13,824

RAM kbits (1,024 bits)

108

4,608-Bit Blocks

FlashROM Kbits

Secure (AES) ISP

Yes

Integrated PLL in CCCs

VersaNet Globals

I/O Banks

Maximum User I/Os

270

Package Pins

VQFP

VQ100

PQFP

FBGA

FG484

Notes:

1. Refer to the

Cortex-M1

product brief for more information.

2. AES is not available for ARM-enabled ProASIC3/EL devices.

† A3P250 and A3P1000 support only 1.5 V core operation.

ƒ Flash*Freeze technology is not available for A3P250 or A3P1000.

††Pro I/Os are not available on A3P250 or A3P1000.

September 2012

PQ208

FG144, FG484

FG484, FG896

Military ProASIC3/EL Low Power Flash FPGAs

Table of Contents

Military ProASIC3/EL Device Family Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Military ProASIC3/EL DC and Switching Characteristics

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-112

Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-121

Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-125

Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-127

Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-148

JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-149

Pin Descriptions and Packaging

Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

User-Defined Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1

3-2

3-4

3-5

Package Pin Assignments

VQ100

PQ208

FG144

FG484

FG896

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

Revision 3

M1A3P1000-2FG256 Related Products

	M1A3P1000-2FG256	M1A3P1000-1PQ208	M1A3P1000-2FGG256	M1A3P1000-FGG484I	M1A3P1000-FG484I
Description	FPGA - Field Programmable Gate Array ProASIC3	FPGA - Field Programmable Gate Array ProASIC3		FPGA - Field Programmable Gate Array ProASIC3
Is it Rohs certified?	incompatible	incompatible	conform to	conform to	incompatible
package instruction	BGA,	FQFP,	BGA,	BGA,	BGA,
Reach Compliance Code	compliant	compliant	compliant	compliant	unknown
maximum clock frequency	350 MHz	350 MHz	350 MHz	350 MHz	350 MHz
JESD-30 code	S-PBGA-B256	S-PQFP-G208	S-PBGA-B256	S-PBGA-B484	S-PBGA-B484
length	17 mm	28 mm	17 mm	23 mm	23 mm
Humidity sensitivity level	3	3	3	3	3
Configurable number of logic blocks	24576	24576	24576	24576	24576
Equivalent number of gates	1000000	1000000	1000000	1000000	1000000
Number of terminals	256	208	256	484	484
Maximum operating temperature	85 °C	85 °C	85 °C	100 °C	100 °C
organize	24576 CLBS, 1000000 GATES	24576 CLBS, 1000000 GATES	24576 CLBS, 1000000 GATES	24576 CLBS, 1000000 GATES	24576 CLBS, 1000000 GATES
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	FQFP	BGA	BGA	BGA
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	FLATPACK, FINE PITCH	GRID ARRAY	GRID ARRAY	GRID ARRAY
Peak Reflow Temperature (Celsius)	225	225	260	250	225
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.8 mm	4.1 mm	1.8 mm	2.44 mm	2.44 mm
Maximum supply voltage	1.575 V	1.575 V	1.575 V	1.575 V	1.575 V
Minimum supply voltage	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V
Nominal supply voltage	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	TIN LEAD/TIN LEAD SILVER	Tin/Lead (Sn/Pb)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Lead (Sn/Pb)
Terminal form	BALL	GULL WING	BALL	BALL	BALL
Terminal pitch	1 mm	0.5 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	QUAD	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	30	30	40	40	30
width	17 mm	28 mm	17 mm	23 mm	23 mm
JESD-609 code	-	e0	e1	e1	e0
Maker	-	-	Microsemi	Microsemi	Microsemi

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