S25FL128SAGBHVB00 datasheet, PDF

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S25FL128SAGBHVB00: DescriptionFlash Memory Nor; Categorystorage storage; File Size229KB，10 Pages; ManufacturerCypress Semiconductor; Environmental Compliance

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Flash Memory Nor

S25FL128SAGBHVB00 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Cypress Semiconductor
package instruction	TBGA, BGA24,5X5,40
Reach Compliance Code	compliant
ECCN code	3A991.B.1.A
Other features	ALSO CONFIGURABLE AS 128M X 1
Spare memory width	2
startup block	BOTTOM
Maximum clock frequency (fCLK)	133 MHz
Data retention time - minimum	20
Durability	100000 Write/Erase Cycles
JESD-30 code	R-PBGA-B24
length	8 mm
memory density	134217728 bit
Memory IC Type	FLASH
memory width	4
Number of functions	1
Number of terminals	24
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	105 °C
Minimum operating temperature	-40 °C
organize	32MX4
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Encapsulate equivalent code	BGA24,5X5,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3/3.3 V
Programming voltage	3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Serial bus type	SPI
Maximum standby current	0.0003 A
Maximum slew rate	0.1 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
type	NOR TYPE
width	6 mm
Maximum write cycle time (tWC)	500 ms
write protect	HARDWARE/SOFTWARE
Base Number Matches	1

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SUPPLEMENT

S25FL128S

S25FL256S

128 Mbit (16 Mbyte) and

256 Mbit (32 Mbyte), 3 V, MirrorBit

Flash

This supplementary document provides information on a device designed for limited distribution. It describes how the features,

operation, and ordering options of this device have been enhanced or changed from the standard device on which it is based. The

information contained in this document modifies any information on the same topics established by the data sheets listed in the

Affected Documents/Related Documents table and should be used in conjunction with those documents. This document may also

contain information that was not previously covered by the S25FL128S and S25FL256S data sheets. It is intended for hardware

system designers and software developers of applications, operating systems, or tools.

General Description

Affected Documents/Related Documents

Title

S25FL128S and S25FL256S Data Sheet

Spansion Publication Number

S25FL128S_256S_00

Cypress Document Number

001-98283

Cypress Semiconductor Corporation

Document Number: 002-00627 Rev. *D

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised June 09, 2017

SUPPLEMENT

S25FL128S

S25FL256S

(TBPROT = 0) or to Ones (TBPROT = 1) to select the lowest or highest address main Flash array address range per the table below.

When TBPROT is cleared to a 0, the bottom (zero address) 64 kB or 256 kB of the array is readable. When TBPROT is set to a 1,

the top (maximum address) 64 kB or 256 kB of the array is readable. The selection of 64 kB or 256 kB depends on the OPN

selection for size of the sector erase command.

Sector size option

64 kB (Hybrid)

256 kB (Uniform)

TBPARM is ignored

TBPARM = 0 (bottom of the chip)

TBPROT = 0

User is confined to the lowest

address sixteen 4 kB sectors.

User is confined to the lowest

address sector

TBPROT = 1

User is confined to the highest

address 64 kB sector

User is confined to highest

address sector

TBPARM = 1 (top of the chip)

TBPROT = 0

User is confined to the lowest

address 64 kB sector

User is confined to the lowest

address sector

TBPROT = 1

User is confined to the highest

address sixteen 4 kB sectors

User is confined to highest

address sector

This address range selection is independent of the bank address register. The Bank Address Register remains at the default value

of zero. The BRWR command does not work during read password mode so the user must be aware to set the BAR to the desired

address immediately after the password unlock to normal read mode.

The PPB bits are protected from program and erase when PPB Lock is 0 and may be programmed or erased when PPB Lock is 1.

The PPB Lock bit is set to 0 by power-on reset or hardware reset — same as in PPB Password Protection Mode.

Read Password Protection Notes:

1. The user can program the ASPR[5] bit to 0 and use read password, or not, as desired.

2. The command sequence for programming, reading, and locking of the Password for Read Password Method is the same

as the default for the PPB Password Method.

3. When the Read Password Mode and Password Protection Mode are enabled (i.e. ASPR[2] and ASPR[5] are

programmed to 0), then all addresses are redirected to the Boot Sector until the password unlocking sequence is properly

entered, with the correct password. At which time, the Read Password Mode is disabled and all addressing will select the

proper location.

4. If a system hardware reset occurs, then the Read Password Mode is re-enabled.

5. ASPR[5] is used to select between Read Password vs. PPB Password options. If ASPR[5]=0 then the device is ready for

Read Password. However, Read Password is not enabled until ASPR[2]=0. At which point, all addresses select only

within the top or bottom sectors, until the device is unlocked with the proper unlocking sequence and Password. When

ASPR[2] is not = 1 the addresses select normally. This allows users to program in code, test it, provide a password, and

then lock it by programming ASPR[2]= 0.

6. The PLBWR command has undefined results if sent when Read Password Protection is in use. The PPB Lock bit may

only be returned to 0 by a hardware reset or power-on reset.

7. Only the read commands and the Password Unlock command are valid during Read Password Mode while the PPB Lock

bit = 1. Other commands are disabled until the password is supplied to enable reading of the entire device and normal

command operation.

8. When Read Password Protection mode is active (ASPR[5]=0, ASPR[2]=0, PPB Lock = 0), reading of the main array is

allowed but forced to have only the boot sector visible via the forcing of memory sector address to zero or ones. Reading

the OTP, DYB, and PPB address space returns undefined data.

9. Programming memory spaces or writing registers is not allowed when Read Password Protection mode is active. The

WRR, WRDI, WREN, ABWR, BRWR, ASPP, CLSR, OTPP, PNVDLR, WVDLR, PLBWR, DYBWR, PPBP, PPBE and

PASSP commands do not change memory or register state when Read Password Protection mode is active. RESET

operates normally, and bus protocol may be modified by resetting mode bits.

10. AutoBoot is disabled when the Read Password feature is enabled, as part of the ASP. This removes any conflicts when

the AutoBoot address is within the Protected Area. The user won’t be able to AutoBoot since a password is required prior

to addressing the “boot” code. Cypress recommends that the ABE Bit 0 should be cleared to 0 when the Read Password

feature is enabled.

11. All ID Read commands - ABh, 90h, 9Fh, and 5Ah (FL512S only) - are enabled and can be used when the device is in

Read Password Protection mode.

Document Number: 002-00627 Rev. *D

Page 4 of 8

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