CY7C144E-55JXCT datasheet, PDF

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CY7C144E-55JXCT: Categorystorage; File Size2MB，23 Pages; ManufacturerCypress Semiconductor

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CY7C144E-55JXCT Parametric

Parameter Name	Attribute value
Product Category	SRAM
Manufacturer	Cypress Semiconductor
RoHS	Details
Memory Size	64 kbit
Organization	8 k x 8
Access Time	15 ns
Interface Type	Parallel
Supply Voltage - Max	5.5 V
Supply Voltage - Min	4.5 V
Supply Current - Max	180 mA
Minimum Operating Temperature	0 C
Maximum Operating Temperature	+ 70 C
Mounting Style	SMD/SMT
Package / Case	PLCC-68
Packaging	Reel
Memory Type	SDR
Factory Pack Quantity	250
Type	Asynchronous
Unit Weight	0.171777 oz

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CY7C144E

8K × 8 Dual-Port Static RAM

with SEM, INT, BUSY

8K × 8 Dual-Port Static RAM with SEM, INT, BUSY

Features

■

Functional Description

The CY7C144E is a high speed CMOS 8K × 8 dual port static

RAM. Various arbitration schemes are included on the

CY7C144E to handle situations when multiple processors

access the same piece of data. Two ports are provided permitting

independent, asynchronous access for reads and writes to any

location in memory. The CY7C144E can be used as a

standalone 64-Kbit dual-port static RAM or multiple devices can

be combined in order to function as a 16-bit or wider

master/slave dual-port static RAM. An M/S pin is provided for

implementing 16-bit or wider memory applications without the

need for separate master and slave devices or additional

discrete

logic.

Application

areas

include

interprocessor/multiprocessor designs, communications status

buffering, and dual-port video / graphics memory.

Each port has independent control pins: chip enable (CE), read

or write enable (R/W), and output enable (OE). Two flags, BUSY

and INT, are provided on each port. BUSY signals that the port

is trying to access the same location currently being accessed

by the other port. The interrupt flag (INT) permits communication

between ports or systems by means of a mail box. The

semaphores are used to pass a flag, or token, from one port to

the other to indicate that a shared resource is in use. The

semaphore logic is comprised of eight shared latches. Only one

side can control the latch (semaphore) at any time. Control of a

semaphore indicates that a shared resource is in use. An

automatic power-down feature is controlled independently on

each port by a chip enable (CE) pin or SEM pin.

For a complete list of related documentation, click

here.

True dual-ported memory cells that enable simultaneous reads

of the same memory location

8K × 8 organization (CY7C144E)

0.35-micron CMOS for optimum speed and power

High-speed access: 15 ns

Low operating power: I

= 180 mA (typical),

standby ISB3 = 0.05 mA (typical)

Fully asynchronous operation

Automatic power-down

TTL compatible

Master / slave select pin enables bus width expansion to 16-bits

or more

Busy arbitration scheme provided

Semaphores included to permit software handshaking

between ports

INT flag for port-to-port communication

Available in 68-pin PLCC and 64-pin TQFP

Pb-free packages available

Logic Block Diagram

R/W

I/O

BUSY

[1, 2]

12L

ADDRESS

DECODER

I/O

CONTROL

I/O

CONTROL

I/O

BUSY

[1, 2]

12R

MEMORY

ARRAY

ADDRESS

DECODER

R/W

SEM

INT

[2]

INTERRUPT

SEMAPHORE

ARBITRATION

R/W

SEM

INT

[2]

M/S

Notes

1. BUSY is an output in master mode and an input in slave mode.

2. Interrupt: push-pull output and requires no pull-up resistor.

Cypress Semiconductor Corporation

Document Number: 001-63982 Rev. *D

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised February 16, 2017

CY7C144E

Contents

Selection Guide ................................................................ 3

Pin Configuration ............................................................. 3

Pin Definitions .................................................................. 4

Architecture ...................................................................... 4

Functional Overview ........................................................ 5

Write Operation ........................................................... 5

Read Operation ........................................................... 5

Interrupts ..................................................................... 5

Busy ............................................................................ 5

Master/Slave ............................................................... 6

Semaphore Operation ................................................. 6

Maximum Ratings ............................................................. 7

Operating Range ............................................................... 7

Electrical Characteristics ................................................. 7

Capacitance ...................................................................... 8

AC Test Loads and Waveforms ....................................... 8

Switching Characteristics ................................................ 9

Switching Waveforms .................................................... 11

Typical DC and AC Characteristics .............................. 17

Ordering Information ...................................................... 18

Ordering Code Definitions ......................................... 18

Package Diagrams .......................................................... 19

Acronyms ........................................................................ 21

Document Conventions ................................................. 21

Units of Measure ....................................................... 21

Document History Page ................................................. 22

Sales, Solutions, and Legal Information ...................... 23

Worldwide Sales and Design Support ....................... 23

Products .................................................................... 23

PSoC® Solutions ...................................................... 23

Cypress Developer Community ................................. 23

Technical Support ..................................................... 23

Document Number: 001-63982 Rev. *D

Page 2 of 23

CY7C144E-55JXCT Related Products

	CY7C144E-55JXCT	CY7C144E-55AXC
Description		SRAM 64Kb (8Kb x 8) 55ns Dual-Port SRAM
Product Category	SRAM	SRAM
Manufacturer	Cypress Semiconductor	Cypress Semiconductor
RoHS	Details	Details
Memory Size	64 kbit	64 kbit
Organization	8 k x 8	8 k x 8
Access Time	15 ns	15 ns
Interface Type	Parallel	Parallel
Supply Voltage - Max	5.5 V	5.5 V
Supply Voltage - Min	4.5 V	4.5 V
Supply Current - Max	180 mA	180 mA
Minimum Operating Temperature	0 C	0 C
Maximum Operating Temperature	+ 70 C	+ 70 C
Mounting Style	SMD/SMT	SMD/SMT
Package / Case	PLCC-68	TQFP-64
Packaging	Reel	Tray
Memory Type	SDR	SDR
Factory Pack Quantity	250	90
Type	Asynchronous	Asynchronous
Unit Weight	0.171777 oz	0.012720 oz

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