SY89468U
Precision LVDS 1:20 Fanout with 2:1 MUX
and Internal Termination with Fail-Safe Input
General Description
The SY89468U is a 2.5V, 1:20 LVDS fanout buffer
with a 2:1 differential input multiplexer (MUX). A
unique Fail-Safe Input (FSI) protection prevents
metastable output conditions when the selected
input clock fails to a DC voltage (voltage between
the pins of the differential input drops significantly
below 100mV).
The differential input includes Micrel’s unique, 3-pin
internal termination architecture that can interface to
any differential signal (AC- or DC-coupled) as small
as 100mV (200mV
PP
) without any level shifting or
termination resistor networks in the signal path. The
outputs are LVDS compatible with very fast rise/fall
times guaranteed to be less than 270ps.
The SY89468U operates from a 2.5V ±5% supply
and is guaranteed over the full industrial
temperature range of –40°C to +85°C. The
SY89468U is part of Micrel’s high-speed, Precision
®
Edge product line.
All support documentation can be found on Micrel’s
web site at:
www.micrel.com.
Precision Edge
®
Features
∑
Selects between two inputs, and provides 20
precision LVDS copies
∑
Fail-Safe Input
– Prevents outputs from oscillating when input is
invalid
∑
Guaranteed AC performance over temperature and
supply voltage:
– DC to >1.5GHz throughput
– < 1200ps Propagation Delay (In-to-Q)
– < 270ps Rise/Fall times
∑
Ultra-low jitter design:
– <1ps
RMS
random jitter
– <1ps
RMS
cycle-to-cycle jitter
– <10ps
PP
total jitter (clock)
– <0.7ps
RMS
MUX crosstalk induced jitter
∑
Unique, patented MUX input isolation design
minimizes adjacent channel crosstalk
∑
Unique, patented internal termination and VT pin
accepts DC- and AC-coupled inputs (CML, PECL,
LVDS)
∑
Wide input voltage range VCC to GND
∑
2.5V ±5% supply voltage
∑
-40°C to +85°C industrial temperature range
∑
Available in 64-pin EPAD-TQFP package
Functional Block Diagram
Applications
∑
Fail-safe clock protection
∑
Ultra-low jitter LVDS clock or data distribution
∑
Rack-based Telecom/Datacom
Markets
∑
∑
∑
∑
LAN/WAN
Enterprise servers
ATE
Test and measurement
United States Patent No. RE44,134
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame
and MLF are registered trademarks of Amkor Technology, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
November 2008
M9999-110308-D
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89468U
Ordering Information
(1)
Part Number
SY89468UHY
SY89468UHYTR
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals Only.
2. Tape and Reel.
(2)
Package
Type
H64-1
H64-1
Operating
Range
Industrial
Industrial
Package Marking
SY89468UHY with
Pb-Free bar-line Indicator
SY89468UHY with
Pb-Free bar-line Indicator
Lead
Finish
Matte-Sn
Pb-Free
Matte-Sn
Pb-Free
Pin Configuration
64-Pin EPAD-TQFP (H64-1)
November 2008
2
M9999-110308-D
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89468U
Pin Description
Pin Number
1, 16, 23, 33
41, 48, 58
64, 63
62, 61
60, 59
57, 56
55, 54
53, 52
51, 50
47, 46
45, 44
43, 42
39, 38
37, 36
35, 34
31, 30
29, 28
27, 26
25, 24
22, 21
20, 19
18, 17
Pin Name
VCC
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
Q4, /Q4
Q5, /Q5
Q6, /Q6
Q7, /Q7
Q8, /Q8
Q9, /Q9
Q10, /Q10
Q11, /Q11
Q12, /Q12
Q13, /Q13
Q14, /Q14
Q15, /Q15
Q16, /Q16
Q17, /Q17
Q18, /Q18
Q19, /Q19
VREF-AC0
VREF-AC1
Pin Function
Positive Power Supply: Bypass with 0.1µF||0.01µF low ESR capacitors as close to the V
CC
pins as possible.
Differential Output Pairs: The output swing is typically 325mV. Used and unused outputs
must be terminated with 100Ω across the pair (Q, /Q). These differential LVDS outputs are a
logic function of the IN0, IN1, and SEL inputs. See “Truth Table” below.
4, 13
Reference Voltage: These outputs bias to V
CC
–1.2V. They are used for AC-coupling inputs
IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01µF low
ESR capacitor to VCC. Due to limited drive capability, each VREF-AC pin is only intended to
drive its respective VT pin. Maximum sink/source current is ±0.5mA. See “Input Interface
Applications” subsection.
Input Termination Center-Tap: Each side of a differential input pair terminates to the VT pin.
The VT pin provides a center-tap for each input (IN, /IN) to a termination network for
maximum interface flexibility. See “Input Interface Applications” subsection.
Differential Inputs: These input pairs are the differential signal inputs to the device. These
inputs accept AC- or DC-coupled signals as small as 100mV. The input pairs internally
terminate to a VT pin through 50Ω. Each input has level shifting resistors of 3.72kΩ to VCC.
This allows a wide input voltage range from VCC to GND. See Figure 3, Simplified
Differential Input Stage for details. Note that when these inputs are left in an open state, the
FSI feature will override this input state and provide a valid state at the output. See
“Functional Description” subsection.
Ground. Exposed pad must be connected to a ground plane that is the same potential as
the ground pins.
Single-Ended Input: This TTL/CMOS input disables and enables the Q0-Q19 outputs. It is
internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left
open. When disabled, Q goes LOW and /Q goes HIGH. OE being synchronous, outputs will
be enabled/disabled following a rising and a falling edge of the input clock. V
TH
= V
CC
/2.
Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the inputs to the
multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor and will
default to logic HIGH state if left open. V
TH
= V
CC
/2.
5, 12
VT0, VT1
6, 7
10, 11
IN0, /IN0
IN1, /IN1
2, 3, 14, 15,
32, 40, 49
9
GND,
Exposed Pad
OE
8
SEL
Truth Table
Inputs
IN0
0
1
X
X
/IN0
1
0
X
X
IN1
X
X
0
1
/IN1
X
X
1
0
SEL
0
0
1
1
Outputs
Q
0
1
0
1
/Q
1
0
1
0
M9999-110308-D
hbwhelp@micrel.com
or (408) 955-1690
November 2008
3
Micrel, Inc.
SY89468U
Absolute Maximum Ratings
(1)
Supply Voltage (V
CC
) ............................ –0.5V to +4.0V
Input Voltage (V
IN
) ....................................–0.5V to V
CC
LVDS Output Current (I
OUT
)…………………….±10mA
Current (V
T
)
Source or sink on VT pin .......................... ±100mA
Input Current
Source or sink current on (IN, /IN) ............. ±50mA
Current (V
REF
)
(4)
Source/Sink Current on V
REF-AC
............. ±0.5mA
Maximum operating Junction Temperature….. 125°C
Lead Temperature (soldering, 20 sec.)............ +260°C
Storage Temperature (T
s
) ...................–65°C to 150°C
Operating Ratings
(2)
Supply Voltage (V
CC
) ....................+2.375V to +2.625V
Ambient Temperature (T
A
)……………-40°C to +85°C
(3)
Package Thermal Resistance
TQFP (q
JA
)
Still-Air ........................................................ 35°C/W
TQFP (y
JB
)
Junction-to-Board ...................................... 21°C/W
DC Electrical Characteristics
(5)
T
A
= –40°C to +85°C, unless otherwise stated.
Symbol
V
CC
I
CC
R
IN
R
DIFF_IN
V
IH
V
IL
V
IN
V
DIFF_IN
V
IN_FSI
V
REF-AC
V
T_IN
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is
not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB.
q
JA
and
y
JB
values are determined for a 4-layer board in still air unless otherwise stated.
4. Due to limited drive capability use for input of the same package only.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. V
IN
(max) is specified when V
T
is floating.
Parameter
Power Supply
Power Supply Current
Input Resistance
(IN-to-V
T
)
Differential Input Resistance
(IN-to-/IN)
Input High Voltage
(IN, /IN)
Input Low Voltage
(IN, /IN)
Input Voltage Swing
(IN, /IN)
Differential Input Voltage Swing
|IN-/IN|
Input Voltage Threshold that
Triggers FSI
Output Reference Voltage
Voltage from Input to V
T
Condition
Min
2.375
Typ
2.5
260
Max
2.625
365
55
110
V
CC
V
IH
–0.1
1.0
Units
V
mA
Ω
Ω
V
V
V
V
No load, max V
CC
45
90
0.1
0
See Figure 2a. Note 6.
See Figure 2b.
0.1
0.2
50
100
30
I
VREF-AC
= + 0.5mA
V
CC
–1.3
V
CC
–1.2
100
V
CC
–1.1
1.28
mV
V
V
November 2008
4
M9999-110308-D
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89468U
LVDS Outputs DC Electrical Characteristics
(7)
V
CC
= +2.5V ±5%, R
L
= 100_ across the outputs; T
A
= –40°C to +85°C, unless otherwise stated.
Symbol
V
OUT
V
DIFF_OUT
V
OCM
DV
OCM
Parameter
Output Voltage Swing (Q, /Q)
Differential Output Voltage Swing |Q – /Q|
Output Common Mode Voltage (Q, /Q)
Change in Common Mode Voltage (Q, /Q)
Condition
See Figure 2a
See Figure 2b
See Figure 5a
See Figure 5b
Min
250
500
1.125
–50
Typ
325
650
1.20
1.275
+50
Max
Units
mV
mV
V
mV
LVTTL/CMOS DC Electrical Characteristics
(7)
V
CC
= 2.5V ±5%; T
A
= –40°C to + 85°C, unless otherwise stated.
Symbol
V
IH
V
IL
I
IH
I
IL
Note:
7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Condition
Min
2.0
Typ
Max
0.8
Units
V
V
µA
µA
-125
-300
30
November 2008
5
M9999-110308-D
hbwhelp@micrel.com
or (408) 955-1690
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