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871002AGI-02LFT

Description
Clock Synthesizer / Jitter Cleaner Differential-to-0.7V HCSL Jitter Atten
Categorysemiconductor    Analog mixed-signal IC   
File Size339KB,17 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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871002AGI-02LFT Overview

Clock Synthesizer / Jitter Cleaner Differential-to-0.7V HCSL Jitter Atten

871002AGI-02LFT Parametric

Parameter NameAttribute value
Product CategoryClock Synthesizer / Jitter Cleaner
ManufacturerIDT (Integrated Device Technology, Inc.)
RoHSDetails
Package / CaseTSSOP-20
PackagingReel
Height1 mm
Length6.5 mm
Factory Pack Quantity2500
Width4.4 mm
Differential-to-0.7V HCSL Differential PCI
EXPRESS™ Jitter Attenuator
General Description
The 871002I-02 is a high performance Jitter Attenuator designed for
use in PCI Express™ systems. In some PCI Express systems, such
as those found in desktop PCs, the PCI Express clocks are
generated from a low bandwidth, high phase noise PLL frequency
synthesizer. In these systems, a jitter attenuator may be required to
attenuate high frequency random and deterministic jitter components
from the PLL synthesizer and from the system board. The
871002I-02 has two PLL bandwidth modes: 350kHz and 2200kHz.
The 350kHz mode provides the maximum jitter attenuation, but it also
results in higher PLL tracking time. In this mode, the spread spectrum
modulation may also be attenuated. The 2200kHz bandwidth
provides the best tracking skew and will pass most spread profiles,
but the jitter attenuation will not be as good as the lower bandwidth
modes. The 871002I-02 can be set for different modes using the
F_SELx pins as shown in Table 3C.
The 871002I-02 uses IDT 3
rd
Generation FemtoClock
TM
PLL
technology to achieve the lowest possible phase noise. The
device is packaged in a small 20 Lead TSSOP package, making it
ideal for use in space constrained applications such as PCI Express
add-in cards.
871002I-02
DATA SHEET
Features
Two 0.7V HCSL differential output pairs
One differential clock input
CLK, nCLK can accept the following differential input levels:
LVPECL, LVDS, HSTL, HCSL, SSTL
Input frequency range: 98MHz to 128MHz
Output frequency range: 98MHz to 640MHz
VCO range: 490MHz - 640MHz
Cycle-to-cycle jitter: 45ps (maximum)
Two bandwidth modes allow the system designer to make jitter
attenuation/tracking skew design trade-offs
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
PLL Bandwidth (typical) Table
BW_SEL
0 = PLL Bandwidth: ~350kHz (default)
1 = PLL Bandwidth: ~2200kHz
Block Diagram
IREF
OE
Pullup
F_SEL[1:0]
Pullup:Pulldown
2
Pin Assignment
nQ0
IREF
FB_OUT
nFB_OUT
MR
BW_SEL
F_SEL1
V
DDA
F_SEL0
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
V
DD
Q1
nQ1
nFB_IN
FB_IN
GND
nCLK
CLK
OE
BW_SEL
Pulldown
0 = 350kHz
1 = 2200kHz
CLK
Pulldown
nCLK
Pullup
Phase
Detector
VCO
490 - 640 MHz
Output Divider
00 ÷5
01 ÷4
10 ÷2 (default)
11 ÷1
Q0
nQ0
Q1
nQ1
FB_IN
Pulldown
nFB_IN
Pullup
871002I-02
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
÷5 (fixed)
FB_OUT
nFB_OU
MR
Pulldown
871002I-02 Rev A 7/13/15
1
©2015 Integrated Device Technology, Inc.
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