DATASHEET
AC’97 2.3 CODECS WITH STEREO MICROPHONE
& UNIVERSAL JACK
FEATURES
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High Performance
SD
Technology
AC’97 Rev 2.3 Complaint
20-bit Full Duplex Stereo ADC & DACs
Independent Sample Rates for ADC & DACs
5-Wire AC-Link Protocol Compliance
20-Bit SPDIF Output
Universal Jacks
™
Full Stereo Microphone Pre-Amp
Internal Jack Sensing on Headphone & Line_Out
Internal Microphone Input Sensing
Digital PC Beep Option
Extended AC’97 2.3 Paging Registers
General Purpose I/Os and Crystal Elimination
Circuit
Headphone Drive Capability (50 mW per channel)
Switchable Headphone Out (pins 39/41 or 35/36)
0dB, 10dB, 20dB and 30dB Microphone Boost
Capability
+3.3 V (STAC9753A) and +5 V (STAC9752A) Analog
Power Supply Options
Pin Compatible with STAC9750/52/66
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STAC9752A/9753A
Reference Designs
DESCRIPTION
TSI's STAC9752A/9753A are general purpose 20-bit, full
duplex, audio CODECs conforming to the analog compo-
nent specification of AC'97 (Audio CODEC 97 Component
Specification Rev. 2.3). The STAC9752A/9753A incorpo-
rates TSI's proprietary SD technology.
The AC’97 CODEC is designed to achieve a DAC SNR in
excess of 94dB. The DACs, ADCs, and mixer are inte-
grated with analog I/Os, which include four analog
line-level stereo inputs, two analog line-level mono inputs,
two stereo outputs, and one mono output channel.
The STAC9752A/9753A includes digital input/output capa-
bility for support of modern PC systems, with an output that
supports the SPDIF format. The STAC9752A/9753A is a
standard 2-channel stereo CODEC. With TSI’s headphone
drive capability, headphones can be driven with without an
external amplifier.
The STAC9752A/9753A may be used as a secondary
CODEC, with the STAC9700/21/56/08/84/50/52 as the pri-
mary, in a multiple CODEC configuration conforming to the
AC'97 Rev. 2.3 specification. This configuration can provide
the true six-channel, AC-3 playback required for DVD appli-
cations.
The STAC9752A/9753A communicates via the five-wire
AC-Link to any digital component of AC'97, providing flexi-
bility in the audio system design.
Packaged in an AC'97 compliant 48-pin TQFP, the
STAC9752A/9753A can be placed on a motherboard,
daughter boards, PCI, AMR, CNR, MDC or ACR cards.
The STAC9752A/9753A provides variable sample rate Dig-
ital-to-Analog (DA) and Analog-to-Digital (AD) conversion,
mixing, and analog processing.
Supported audio sample rates include 48 KHz, 44.1 KHz,
32 KHz, 22.05 KHz, 16 KHz, 11.025 KHz, and 8 KHz; addi-
tional rates are supported in the STAC9752A/9753A soft
audio drivers. All ADCs and DACs operate at 20-bit resolu-
KEY SPECIFICATIONS
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Analog LINE_OUT SNR: 94dB
Digital DAC SNR: 92dB
Digital ADC SNR: 85dB
Full-scale Total Harmonic Distortion: 0.002%
Crosstalk Between Input Channels: -70dB
Spurious Tone Rejection: 100dB
Stereo Microphone Input
RELATED MATERIALS
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Data Sheet
TSI™ CONFIDENTIAL
©2014 TEMPO SEMICONDCUTOR, INC.
1
V 1.6 10/14
STAC9752A/9753A
STAC9752A/9753A
AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
TABLE OF CONTENTS
PRODUCT BRIEF ......................................................................................................................... 6
Features ....................................................................................................................................................6
Description ................................................................................................................................................6
STAC9752A/9753A Block Diagram ..........................................................................................................8
Key Specifications ....................................................................................................................................8
Related Materials ......................................................................................................................................8
Additional Support ....................................................................................................................................9
CHARACTERISTICS AND SPECIFICATIONS ........................................................................... 10
Electrical Specifications ..........................................................................................................................10
Absolute Maximum Ratings .........................................................................................................10
Recommended Operation Conditions .........................................................................................10
Power Consumption ....................................................................................................................11
AC-Link Static Digital Specifications ............................................................................................11
STAC9752A Analog Performance Characteristics .......................................................................12
STAC9753A Analog Performance Characteristics .......................................................................13
AC Timing Characteristics ......................................................................................................................15
Cold Reset ...................................................................................................................................15
Warm Reset .................................................................................................................................15
Clocks ..........................................................................................................................................16
STAC9752A/9753A Crystal Elimination Circuit and Clock Frequencies ......................................16
Data Setup and Hold ...................................................................................................................17
Signal Rise and Fall Times ..........................................................................................................17
AC-Link Low Power Mode Timing ................................................................................................18
ATE Test Mode ............................................................................................................................18
TYPICAL CONNECTION AND POWER DIAGRAMS ................................................................. 20
STAC9752A/9753A Typical Connection Diagram for 48-pin LQFP ........................................................20
STAC9752A/9753A Typical Connection Diagram for 32-pad QFN ........................................................21
Split Independent Power Supply Operation ............................................................................................22
Split Independent Power Supply Operation for the 32-pad QFP Package .............................................23
CONTROLLER, CODEC, AND AC-LINK .................................................................................... 24
AC-Link Physical interface ......................................................................................................................24
Controller to Single CODEC ...................................................................................................................24
Controller to Multiple CODECs ...............................................................................................................25
Primary CODEC Addressing ........................................................................................................25
Secondary CODEC Addressing ...................................................................................................26
CODEC ID Strapping .....................................................................................................................6
Clocking for Multiple CODEC Implementations ......................................................................................26
STAC9752A/9753A as a Primary CODEC .............................................................................................26
STAC9752A/9753A as a Secondary CODEC ..............................................................................27
AC-Link Power Management ..................................................................................................................27
Powering down the AC-Link .........................................................................................................27
Waking up the AC-Link ................................................................................................................27
Controller Initiates Wake-up ..........................................................................................28
CODEC Initiates Wake-up .............................................................................................28
CODEC Reset ..............................................................................................................................28
Cold AC‘97 Reset ..........................................................................................................28
Warm AC‘97 Reset ........................................................................................................28
Register AC‘97 Reset ....................................................................................................29
AC-LINK DIGITAL INTERFACE ................................................................................................. 30
Overview .................................................................................................................................................30
AC-Link Serial Interface Protocol ............................................................................................................31
AC-Link Variable Sample Rate Operation ...................................................................................31
Variable Sample Rate Signaling Protocol ....................................................................................31
SLOTREQ Behavior and Power Management ..............................................................32
Primary and Secondary CODEC Register Addressing ................................................................33
AC-Link Output Frame (SDATA_OUT) ...................................................................................................33
Slot 0: TAG / CODEC ID ..............................................................................................................35
TSI™ CONFIDENTIAL
©2014 TEMPO SEMICONDCUTOR, INC.
2
V 1.6 10/14
STAC9752A/9753A
STAC9752A/9753A
AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
Slot 1: Command Address Port ...................................................................................................35
Slot 2: Command Data Port .........................................................................................................36
Slot 3: PCM Playback Left Channel .............................................................................................36
Slot 4: PCM Playback Right Channel ..........................................................................................36
Slot 5: NOT USED (Modem Line 1 Output Channel) ...................................................................36
Slot 6 -11: DAC ............................................................................................................................37
Slot 12: Audio GPIO Control Channel ..........................................................................................37
AC-Link Input Frame (SDATA_IN) ..........................................................................................................37
Slot 0: TAG ..................................................................................................................................38
Slot 1: Status Address Port / SLOTREQ Signaling Bits ...............................................................38
Status Address Port .......................................................................................................38
SLOTREQ signaling bits ................................................................................................38
Slot 2: Status Data Port ...............................................................................................................39
Slot 3: PCM Record Left Channel ................................................................................................39
Slot 4: PCM Record Right Channel .............................................................................................39
Slot 5: NOT USED (Modem Line 1 ADC) .....................................................................................39
Slot 6-9: ADC ...............................................................................................................................39
Slots 7-8: Vendor Reserved .........................................................................................................40
Slot 10 & 11: ADC ........................................................................................................................40
Slot 12: Reserved ........................................................................................................................40
AC-Link Interoperability Requirements and Recommendations .............................................................40
“Atomic slot” Treatment of Slot 1 Address and Slot 2 Data ..........................................................40
Slot Assignments for Audio .....................................................................................................................41
STAC9752A/9753A FUNCTIONAL BLOCKS ............................................................................ 43
STAC9752A/9753A Mixer Description ....................................................................................................43
Mixer Functional Diagrams .........................................................................................................44
Mixer Analog Input .......................................................................................................................44
Mixer Analog Output ....................................................................................................................44
SPDIF Digital Mux ..................................................................................................................................44
PC Beep Implementation ........................................................................................................................45
Analog PC Beep ..........................................................................................................................45
Digital PC Beep ............................................................................................................................45
PROGRAMMING REGISTERS ................................................................................................... 46
Register Descriptions ..............................................................................................................................47
Reset (00h) ..................................................................................................................................47
Master Volume Registers (02h) ...................................................................................................47
Headphone Volume Registers (04h) ............................................................................................48
Master Volume MONO (06h) .......................................................................................................49
PC BEEP Volume (0Ah) ..............................................................................................................49
Phone Volume (Index 0Ch) ..........................................................................................................50
Stereo or Mic Volume (Index 0Eh) ...............................................................................................50
LineIn Volume (Index 10h) ...........................................................................................................51
CD Volume (Index 12h) ...............................................................................................................52
Video Volume (Index 14h) ..........................................................................................................52
Aux Volume (Index 16h) ..............................................................................................................53
PCMOut Volume (Index 18h) .......................................................................................................53
Record Select (1Ah) .....................................................................................................................54
Record Gain (1Ch) .......................................................................................................................55
General Purpose (20h) ................................................................................................................55
3D Control (22h) ..........................................................................................................................56
Audio Interrupt and Paging (24h) .................................................................................................56
Powerdown Ctrl/Stat (26h) ...........................................................................................................57
Ready Status .................................................................................................................58
Powerdown Controls .....................................................................................................58
External Amplifier Power Down Control Output .............................................................58
Extended Audio ID (28h) ..............................................................................................................59
Extended Audio Control/Status (2Ah) ..........................................................................................60
Variable Rate Sampling Enable .....................................................................................61
SPDIF ............................................................................................................................61
TSI™ CONFIDENTIAL
©2014 TEMPO SEMICONDCUTOR, INC.
3
V 1.6 10/14
STAC9752A/9753A
STAC9752A/9753A
AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
SPCV (SPDIF Configuration Valid) ...............................................................................61
SPSA1, SPSA0 (SPDIF Slot Assignment) ....................................................................61
PCM DAC Rate Registers (2Ch and 32h) ....................................................................................62
PCM DAC Rate (2Ch) ..................................................................................................................62
PCM LR ADC Rate (32h) .............................................................................................................62
SPDIF Control (3Ah) ....................................................................................................................63
General Purpose Input & Outputs ...........................................................................................................63
EAPD ...........................................................................................................................................63
GPIO Pin Definitions ....................................................................................................................64
GPIO Pin Implementation ............................................................................................................64
Extended Modem Status and Control Register (3Eh) ..................................................................64
GPIO Pin Configuration Register (4Ch) .......................................................................................65
GPIO Pin Polarity/Type Register (4Eh) ........................................................................................65
GPIO Pin Sticky Register (50h) ...................................................................................................65
GPIO Pin Mask Register (52h) ....................................................................................................66
GPIO Pin Status Register (54h) ...................................................................................................66
Extended CODEC Registers Page Structure Definition ..........................................................................66
Extended Registers Page 00 .......................................................................................................67
Extended Registers Page 01 .......................................................................................................67
Extended Registers Page 02, 03 .................................................................................................67
STAC9752A/9753A Paging Registers ....................................................................................................67
CODEC Class/Rev (60h
Page 01h
) ...........................................................................................67
PCI SVID (62h
Page 01h
) ..........................................................................................................68
PCI SSID (64h
Page 01h
) ..........................................................................................................68
Function Select (66h
Page 01h
) ................................................................................................69
Function Information (68h
Page 01h
) ........................................................................................70
Digital Audio Control (6Ah, Page 00h) .........................................................................................72
Sense Details (6Ah
Page 01h
)................................................................................................... 72
Revision Code (6Ch) ....................................................................................................................74
Analog Special (6Eh) ...................................................................................................................74
Analog Current Adjust (72h) ........................................................................................................75
EAPD Access Register (74h) ....................................................................................................... 76
Register 78h Enable (76h) ...........................................................................................................77
Universal Jacks™ Selection (78h) ...............................................................................................77
Vendor ID1 and ID2 (Index 7Ch and 7Eh) ..............................................................................................78
Vendor ID1 (7Ch) .........................................................................................................................78
Vendor ID2 (7Eh) .........................................................................................................................78
LOW POWER MODES ................................................................................................................ 79
MULTIPLE CODEC SUPPORT ................................................................................................... 81
Primary/Secondary CODEC Selection ....................................................................................................81
Primary CODEC Operation ..........................................................................................................81
Secondary CODEC Operation .....................................................................................................81
Secondary CODEC Register Access Definitions ....................................................................................81
TESTABILITY .............................................................................................................................. 83
ATE Test Mode .......................................................................................................................................83
STAC9752A/9753A PIN DESCRIPTION .................................................................................... 84
Pin Description for the 48-pin LQFP Package ........................................................................................84
Pinout List 48-pin LQFP Package ..........................................................................................................85
Pin Description for the 32-pad QFN Package .........................................................................................86
Pinout List 32-pad QFN Package ..........................................................................................................87
STAC9752A/9753A Digital I/O ................................................................................................................87
STAC9752A/9753A Analog I/O ..............................................................................................................88
STAC9752A/9753A Filter/References ....................................................................................................89
STAC9752A/9753A Power and Ground Signals .....................................................................................89
STAC9752A/9753A No Connects ...........................................................................................................89
ORDERING INFORMATION ....................................................................................................... 90
PACKAGE DRAWINGS AND PC BOARD LAYOUT INFORMATION ....................................... 91
48-Pin LQFP ...........................................................................................................................................91
TSI™ CONFIDENTIAL
©2014 TEMPO SEMICONDCUTOR, INC.
4
V 1.6 10/14
STAC9752A/9753A
STAC9752A/9753A
AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
32-Pad QFN ............................................................................................................................................92
PC Board Recommendations for 32-pad QFN Package 93
SOLDER REFLOW PROFILE ..................................................................................................... 94
Standard Reflow Profile Data .................................................................................................................94
Pb Free Process - Package Classification Reflow Temperatures .........................................................94
APPENDIX A: PROGRAMMING REGISTERS ........................................................................... 96
REVISION HISTORY ................................................................................................................... 98
TSI™ CONFIDENTIAL
©2014 TEMPO SEMICONDCUTOR, INC.
5
V 1.6 10/14
STAC9752A/9753A
Microcontroller MCU
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