PRELIMINARY DATA SHEET
1GB Unbuffered DDR SDRAM DIMM
EBD11UD8ABFB
(128M words
×
64 bits, 2 Banks)
Description
The EBD11UD8ABFB is 128M words
×
64 bits, 2
banks Double Data Rate (DDR) SDRAM unbuffered
module, mounted 16 pieces of 512M bits DDR SDRAM
sealed in TSOP package. Read and write operations
are performed at the cross points of the CK and the
/CK. This high-speed data transfer is realized by the 2
bits prefetch-pipelined architecture. Data strobe (DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. This module provides high
density mounting without utilizing surface mount
technology.
Decoupling capacitors are mounted
beside each TSOP on the module board.
Features
•
184-pin socket type dual in line memory module
(DIMM)
PCB height: 31.75mm
Lead pitch: 1.27mm
•
2.5V power supply
•
Data rate: 333Mbps/266Mbps (max.)
•
2.5 V (SSTL_2 compatible) I/O
•
Double Data Rate architecture; two data transfers per
clock cycle
•
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
•
Data inputs and outputs are synchronized with DQS
•
4 internal banks for concurrent operation
(Component)
•
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
referenced to both edges of DQS
•
Auto precharge option for each burst access
•
Programmable burst length: 2, 4, 8
•
Programmable /CAS latency (CL): 2, 2.5
•
Refresh cycles: (8192 refresh cycles /64ms)
7.8µs maximum average periodic refresh interval
•
2 variations of refresh
Auto refresh
Self refresh
Document No. E0296E20 (Ver. 2.0)
Date Published August 2002 (K) Japan
URL: http://www.elpida.com
Elpida
Memory , Inc. 2002
EBD11UD8ABFB
Pin Description
Pin name
A0 to A12
BA0, BA1
DQ0 to DQ63
/RAS
/CAS
/WE
/CS0, /CS1
CKE0, CKE1
CK0 to CK2
/CK0 to /CK2
DQS0 to DQS7
DM0 to DM7/DQS9 to DQS16
SCL
SDA
SA0 to SA2
VDD
VDDQ
VDDSPD
VREF
VSS
VDDID
NC
Function
Address input
Row address
Column address
Data input/output
Row address strobe command
Column address strobe command
Write enable
Chip select
Clock enable
Clock input
Differential clock input
Input and output data strobe
Input mask
Clock input for serial PD
Data input/output for serial PD
Serial address input
Power for internal circuit
Power for DQ circuit
Power for serial EEPROM
Input reference voltage
Ground
VDD identification flag
No connection
A0 to A12
A0 to A9, A11
Bank select address
Preliminary Data Sheet E0296E20 (Ver. 2.0)
4
EBD11UD8ABFB
Serial PD Matrix
Byte No.
0
1
2
3
4
5
6
7
8
9
Function described
Number of bytes utilized by module
manufacturer
Total number of bytes in serial PD
device
Memory type
Number of row address
Number of column address
Number of DIMM banks
Module data width
Module data width continuation
DDR SDRAM cycle time, CL = 2.5
-6B
-7A, -7B
10
SDRAM access from clock (tAC)
-6B
-7A, -7B
11
12
13
14
15
16
17
18
19
20
21
22
23
DIMM configuration type
Refresh rate/type
Primary SDRAM width
Error checking SDRAM width
SDRAM device attributes:
Minimum clock delay back-to-back
column access
SDRAM device attributes:
Burst length supported
SDRAM device attributes: Number of
banks on SDRAM device
SDRAM device attributes:
/CAS latency
SDRAM device attributes:
/CS latency
SDRAM device attributes:
/WE latency
SDRAM module attributes
SDRAM device attributes: General
Minimum clock cycle time at CL = 2
-6B, -7A
-7B
24
Bit7
1
0
0
0
0
0
0
0
Bit6
0
0
0
0
0
0
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
1
1
Bit5 Bit4
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
1
Bit3
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
Bit2
0
0
1
1
0
0
0
0
1
0
1
0
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
0
0
0
Bit1 Bit0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
Hex value
80H
08H
07H
0DH
0BH
02H
40H
00H
04H
60H
75H
70H
75H
00H
82H
08H
00H
01H
0EH
04H
0CH
01H
02H
20H
C0H
75H
A0H
70H
75H
00H
48H
50H
18ns
20ns
Comments
128 bytes
256 bytes
DDR SDRAM
13
11
2
64
0
SSTL2
6.0ns*
1
7.5ns*
1
0.7ns*
1
0.75ns*
1
None.
7.6µs
×
8
None.
1 CLK
2,4,8
4
2, 2.5
0
1
Differential
Clock
VDD ± 0.2V
7.5ns*
1
10ns*
1
0.7ns*
1
0.75ns*
1
Voltage interface level of this assembly 0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
Maximum data access time (tAC) from
clock at CL = 2
0
-6B
-7A, -7B
0
0
Minimum row precharge time (tRP)
-6B
-7A, -7B
0
0
25 to 26
27
Preliminary Data Sheet E0296E20 (Ver. 2.0)
5
PCB Design
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