EDD5116ADTA-7B datasheet, PDF - EEWORLD Datasheet

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EDD5116ADTA-7B: Description512M bits DDR SDRAM; Categorystorage storage; File Size470KB，49 Pages; ManufacturerELPIDA; Websitehttp://www.elpida.com/en

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EDD5116ADTA-7B Overview

512M bits DDR SDRAM

EDD5116ADTA-7B Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	ELPIDA
Parts packaging code	TSOP2
package instruction	TSSOP, TSSOP66,.46
Contacts	66
Reach Compliance Code	unknow
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	0.75 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	100 MHz
I/O type	COMMON
interleaved burst length	2,4,8
JESD-30 code	R-PDSO-G66
JESD-609 code	e0
length	22.22 mm
memory density	536870912 bi
Memory IC Type	DDR DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	66
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32MX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP66,.46
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	235
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	2,4,8
Maximum standby current	0.003 A
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10.16 mm

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DATA SHEET

512M bits DDR SDRAM

EDD5104ADTA (128M words

4 bits)

EDD5108ADTA (64M words

8 bits)

EDD5116ADTA (32M words

16 bits)

Description

The EDD5104AD, the EDD5108AD and the

EDD5116AD are 512M bits Double Data Rate (DDR)

SDRAM. Read and write operations are performed at

the cross points of the CK and the /CK. This high-

speed data transfer is realized by the 2 bits prefetch-

pipelined architecture. Data strobe (DQS) both for

read and write are available for high speed and reliable

data bus design. By setting extended mode register,

the on-chip Delay Locked Loop (DLL) can be set

enable or disable. It is packaged in standard 66-pin

plastic TSOP (II).

Pin Configurations

/xxx indicates active low signal.

66-pin Plastic TSOP(II)

VDD

DQ0

VDDQ VDDQ VDDQ

DQ1

DQ0

DQ1

DQ2

VSSQ VSSQ VSSQ

DQ3

DQ2

DQ4

VDDQ VDDQ VDDQ

DQ5

DQ1

DQ3

DQ6

VSSQ VSSQ VSSQ

DQ7

VDDQ VDDQ VDDQ

NC LDQS

VDD

LDM

/WE

/CAS

/RAS

/CS

BA0

BA1

A10(AP) A10(AP) A10(AP)

VDD

VSS VSS VSS

DQ15 DQ7 NC

VSSQ VSSQ VSSQ

DQ14 NC

DQ13 DQ6 DQ3

VDDQ VDDQ VDDQ

DQ12 NC

DQ11 DQ5 NC

VSSQ VSSQ VSSQ

DQ10 NC

DQ9 DQ4 DQ2

VDDQ VDDQ VDDQ

DQ8 NC

VSSQ VSSQ VSSQ

UDQS DQS DQS

VREF VREF VREF

VSS VSS VSS

UDM DM

/CK /CK /CK

CKE CKE CKE

A12 A12 A12

A11 A11 A11

VSS VSS VSS

Features

•

Power supply: VDD, VDDQ = 2.5V

0.2V

•

Data Rate: 333Mbps/266Mbps (max.)

•

Double Data Rate architecture; two data transfers per

clock cycle

•

Bi-directional, data strobe (DQS) is transmitted

/received with data, to be used in capturing data at

the receiver

•

Data inputs, outputs, and DM are synchronized with

DQS

•

4 internal banks for concurrent operation

•

DQS is edge aligned with data for READs; center

aligned with data for WRITEs

•

Differential clock inputs (CK and /CK)

•

DLL aligns DQ and DQS transitions with CK

transitions

•

Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

•

Data mask (DM) for write data

•

Auto precharge option for each burst access

•

SSTL_2 compatible I/O

•

Programmable burst length (BL): 2, 4, 8

•

Programmable /CAS latency (CL): 2, 2.5

•

Programmable output driver strength: normal/weak

•

Refresh cycles: 8192 refresh cycles/64ms



7.8µs maximum average periodic refresh interval

•

2 variations of refresh



Auto refresh



Self refresh

Document No. E0384E30 (Ver. 3.0)

Date Published January 2004 (K) Japan

URL: http://www.elpida.com

X 16

(Top view)

A0 to A12

BA0, BA1

DQ0 to DQ15

DQS, LDQS, UDQS

/CS

/RAS

/CAS

/WE

DM, LDM, UDM

/CK

CKE

VREF

VDD

VSS

VDDQ

VSSQ

Address input

Bank select address

Data-input/output

Input and output data strobe

Chip select

Row address strobe command

Column address strobe command

Write enable

Input mask

Clock input

Differential clock input

Clock enable

Input reference voltage

Power for internal circuit

Ground for internal circuit

Power for DQ circuit

Ground for DQ circuit

No connection

Elpida

Memory, Inc. 2003-2004

EDD5104ADTA, EDD5108ADTA, EDD5116ADTA

CONTENTS

Description.....................................................................................................................................................1

Features.........................................................................................................................................................1

Pin Configurations .........................................................................................................................................1

Ordering Information......................................................................................................................................2

Part Number ..................................................................................................................................................2

Electrical Specifications.................................................................................................................................4

Block Diagram .............................................................................................................................................10

Pin Function.................................................................................................................................................11

Command Operation ...................................................................................................................................13

Simplified State Diagram .............................................................................................................................20

Operation of the DDR SDRAM ....................................................................................................................21

Timing Waveforms.......................................................................................................................................40

Package Drawing ........................................................................................................................................46

Recommended Soldering Conditions ..........................................................................................................47

Data Sheet E0384E30 (Ver. 3.0)

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