2. Read and write operations are controlled by the appropriate setting of R/W,
CE
0
, CE
1
,
UB/LB
and
OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4.
ADS
and
REPEAT
are independent of all other memory control signals including
CE
0
, CE
1
and
UB/LB
5. The address counter advances if
CNTEN
= V
IL
on the rising edge of CLK, regardless of all other memory control signals including
CE
0
, CE
1
,
UB/LB.
6. When
REPEAT
is asserted, the counter will reset to the last valid address loaded via
ADS.
This value is not set at power-up: a known location should be loaded via
ADS
during initialization
if desired. Any subsequent
ADS
access during operations will update the
REPEAT
address location.
7. The counter includes bank address and internal address. The counter will advance across bank boundaries. For example, if the counter is in Bank 0, at address FFFh, and is advanced one
location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0. Refer to Timing Waveform of Counter Repeat, page 17. Care
should be taken during operation to avoid having both counters point to the same bank (i.e., ensure BA
0L
- BA
5L
≠
BA
0R
- BA
5R
), as this condition will invalidate the access for both ports.
Please refer to the functional description on page 18 for details.
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