NJU8402
PRELIMINARY
DIGITAL TO ANALOG CONVERTER
FOR STEREO AUDIO
s
GENERAL DESCRIPTION
The
NJU8402
is a 16-bit delta-sigma Digital-to-Analog
Converter for stereo audio. It consists of Serial Audio Data
Interface, Digital Interpolation Filter,
∆Σ
Modulator, SC LPF,
Buffer Amp, System Controller for status control. It
operates on single +5V power supply. Furthermore, it
accepts 16-bit input audio data length or 18-bit, and
supports I
2
S serial data format and LSB justified.
Therefore, the
NJU8402
is suitable for CD, MD, DAT
and other digital audio applications.
s
PACKAGE OUTLINE
NJU8402D
NJU8402M
s
FEATURES
q
q
q
q
q
q
q
q
∆Σ
type 1bit stereo DAC
Sample Rate ( fs ) : 50kHz ( Maximum )
Signal-to-Noise Ratio : 94dB
Input Audio Data Length : 16bits or 18bits
Single ended Analog Output
Internal SC type Low Pass Filter
Operating Voltage +5V
±5%
Package Outline DIP16 / DMP16
s
PIN CONFIGURATION
V
DD
MCKI
SCK
DATA
REQ
AOUTL
VCOML
AV
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
SS
BCLK
LRCK
DIN
RST
AOUTR
VCOM
AV
SS
s
BLOCK DIAGRAM
DIN
BCLK
LRCK
Serial Audio
Data Interface
Digital
Interpolation
Filter
∆Σ
Modulator
∆Σ
Modulator
SC
LPF
SC
LPF
LPF
AOUTL
VCOML
LPF
AOUTR
VCOMR
System
Controller
SCK
REQ
MCKI
RST
DATA
V
SS
AV
DD
AV
SS
V
DD
-1-
NJU8402
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TERMINAL DESCRIPTION
PIN
No.
1
16
8
9
2
13
14
15
SYMBOL
V
DD
V
SS
AV
DD
AV
SS
MCKI
DIN
LRCK
BCLK
INPUT
/OUTPUT
I
I
I
I
FUNCTION
Digital Power Supply, +5V
Digital GND, 0V
Analog Power Supply, +5V
Analog GND, 0V
Master Clock Input Terminal
The input signal frequency is 256 times or 384 times of fs.
Serial Audio Data Input Terminal
L/R Channel Clock Input Terminal
This clock must synchronize with MCKI.
Audio Serial Data Clock Input Terminal
This clock must synchronize with MCKI.
Control Register Serial Data Sift Clock Input Terminal
Control register leads the control data synchronizing the rising edge of SCK
signal. When the control register is not used, the state of SCK terminal has to
keep level ”H”.
Control Register Serial Data Input Terminal
Input data sets various functions.
When the control register is not used, the state of DATA terminal has to keep level
“H”.
Control Register Serial Data Request Input Terminal
The control data are latched in the control register at the rising edge of REQ
signal.
When the control register is not used, the state of REQ terminal has to keep level
“H”.
Reset
“L” level signal into reset terminal initializes the system.
Left channel Analog Signal Common Terminal for Connecting Smooth Capacitor
A chemical capacitor should be connected between this terminal and AV
SS
for
stabilizing.
Right Channel Analog Signal Common Terminal for Connecting Smooth Capacitor
A chemical capacitor should be connected between this terminal and AV
SS
for
stabilizing.
L-Channel Analog Signal Output Terminal
R-Channel Analog Signal Output Terminal
3
SCK
I
4
DATA
I
5
REQ
I
12
7
RST
VCOML
I
O
O
10
6
11
VCOMR
AOUTL
AOUTR
-2-
NJU8402
s
FUNCTION DESCRIPTION
(1-1) Analog Audio Signal Output
Analog signal output is biased in the chip and the maximum amplitude is 0.56
×
AV
DD
. The internal
switched capacitor Low Pass Filter is so effective that the external Low Pass Filters are required only 2-
pole LPF or 3-pole.
(1-2) Serial Data Interface
DIN (Data Input), BCLK (Bit Clock) and LRCK (L/R Clock) are the serial data interface terminals. BCLK is
the bit clock of audio data and IO data are leaded at raising edge of the BCLK. The signal into LRCK
terminal represents the signal for distinguishing between Lch and Rch, and the signal for starting data. The
frequency of LRCK is sampling rate of system ( fs ). The MCIK must be synchronized with LRCK and is
256 times or 384 of fs. The serial data format is complement of 2, MSB-first and compatible with I
2
S serial
data protocol or LSB justified. This serial data format is set by the control register.
LRCK
Left
Right Channel
BCLK
DIN
151413
1 0
151413
1 0
I
2
S serial data format
LRCK
Left
Right Channel
BCLK
DIN
0
1514
2 1 0
1514
2 1 0
LSB justified serial data format
(1-3) System Clock
System Clock into the MCIK terminal must be 256 times or 384 times of fs and synchronizing with LRCK.
This frequency is set by the control register.
(1-4) Reset
The external reset is the asynchronous reset. Reset is released at the falling edge at LRCK. Reset by
command is synchronous which operates as same as the external reset function.
-3-
NJU8402
(1-5) Control Register
The Control Register controls
NJU8402
operation using the serial interface. The SCK terminal is the data
sift clock, the REQ terminal is data request signal, the DATA terminal is the serial data input. The control
data is loaded into the sift register at rising edge of SCK, then it is latched at the rising edge of REQ. The
least 8-bit data, which order is MSB first, is valid for control.
REQ
SCK
DATA
B7
B6
B5
B4
B3
B2
B1
B0
CONTROL PORT TIMING CHART
•
Serial Data Format
B7
0
0
B6
0
0
B5
0
0
B4
0
1
B3
∗
∗
B2
DIF1
∗
B1
DIF0
∗
B0
CLKR
RST
(∗: Don’t Care)
*1 Don't input commands except this table.
0
System Clock
Data Length
Format
Reset
CLKR
DIF0
DIF1
RST
256fs
16
I
2
S
Normal
1
384fs
18
LSB Justified
Reset
Default
0
0
0
*2
*2 The level becomes 0 after initial setting.
-4-
NJU8402
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ABSOLUTE MAXIMUM RATING
(V
SS
=AV
SS
=0V)
PARAMETER
DIGITAL
Power Supply
ANALOG
V
DD
- AV
DD
Input Voltage
Operating Temperature
Storage Temperature
Power Consumption
SYMBOL
V
DD
AV
DD
∆VAVD
VIN
Ta
Tstg
PD
CONDITIONS
−0.3
to+7.0
−0.3
to +7.0
V
DD
- AV
DD
<0.2
−0.3
to V
DD
+ 0.3
−30
to +80
−40
to +125
500（DIP16）
200(DMP16)
UNIT
V
V
V
V
°C
°C
mW
s
RECOMMENDATION OPERATION CONDITION
(V
SS
=AV
SS
=0V)
PARAMETER
Power
Supply
DIGITAL
ANALOG
SYMBOL
V
DD
AV
DD
MIN.
4.75
4.75
CONDITIONS
TYP.
5.0
5.0
MAX.
5.25
5.25
UNIT
V
V
-5-
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