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NJU39610

Description
STEPPER MOTOR CONTROLLER, PQCC28
Categorysemiconductor    Analog mixed-signal IC   
File Size161KB,11 Pages
ManufacturerNew JRC
Websitehttps://www.njr.com
Download Datasheet Parametric View All

NJU39610 Overview

STEPPER MOTOR CONTROLLER, PQCC28

NJU39610 Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals28
Minimum operating temperature-20 Cel
Maximum operating temperature85 Cel
Rated supply voltage5 V
Minimum supply/operating voltage4.75 V
Maximum supply/operating voltage5.25 V
Processing package descriptionPLASTIC, LCC-28
each_compliYes
stateActive
Analog IC other typesSTEPPER MOTOR CONTROLLER
jesd_30_codeS-PQCC-J28
jesd_609_codee0
moisture_sensitivity_level2
Packaging MaterialsPLASTIC/EPOXY
ckage_codeQCCJ
ckage_equivalence_codeLDCC28,.5SQ
packaging shapeSQUARE
Package SizeCHIP CARRIER
eak_reflow_temperature__cel_260
wer_supplies__v_5
qualification_statusCOMMERCIAL
seated_height_max4.7 mm
sub_categoryMotion Control Electronics
surface mountYES
Temperature levelOTHER
terminal coatingTIN LEAD
Terminal formJ BEND
Terminal spacing1.27 mm
Terminal locationQUAD
ime_peak_reflow_temperature_max__s_NOT SPECIFIED
length11.51 mm
width11.51 mm
NJU39610
MICROSTEPPING MOTOR CONTROLLER WITH DUAL DAC
s
GENERAL DESCRIPTION
NJU39610 is a dual 7-bit+sign, Digital-to-Analog Converter
(DAC) especially developed to be used together with the
NJM3771, Precision Stepper Motor driver in micro-stepping
applications. The NJU39610 has a set of input registers
connected to an 8-bit data port for easy interfacing directly to
a microprocessor. The NJU39610 is well suited for high-
speed micro-stepping application.
s
PACKAGE OUTLINE
NJU39610D2
NJU39610FM2
s
FEATURES
• Analog control voltages from 3 V down to 0.0 V
• High-speed microprocessor interface
• Automatic fast/slow current decay control
• Full-scale error
• Fast conversion speed
• Matches NJM3771
• Packages
DIP22/PLCC28
±1
LSB
3
µs
s
BLOCK DIAGRAM
V
DD
V
Ref
NJU39610
WR
C
D
E1
CS
C
D
R
Level 2
DA- Data 1
E
E1
C
D
R
Sign 1
R
Level 1
Digit
Comp
E
CD 1
DA 1
E
E2
A0
E3
C
D
A1
E4
D7 - D0
C
D
R
R
DA- Data 2
D/A
E
D/A
Digit
Comp
E4
C
D
R
DA
E
2
CD 2
E
Sign 2
POR
RESET
R
V
ss
Figure 1. Block Diagram
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