IS61NP12832 IS61NP12836 IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
128K x 32, 128K x 36 and 256K x 18
PIPELINE 'NO WAIT' STATE BUS SRAM
ISSI
®
PRELIMINARY INFORMATION
OCTOBER 2000
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
100 percent bus utilization
No wait cycles between Read and Write
Internal self-timed write cycle
Individual Byte Write Control
Single R/W (Read/Write) control pin
Clock controlled, registered address,
data and control
Interleaved or linear burst sequence control
using MODE input
Three chip enables for simple depth expansion
and address pipelining for TQFP
Power Down mode
Common data inputs and data outputs
CKE
pin to enable clock and suspend operation
JEDEC 100-pin TQFP, 119 PBGA package
Single +3.3V power supply (± 5%)
NP Version: 3.3V I/O Supply Voltage
NLP Version: 2.5V I/O Supply Voltage
Industrial temperature available
DESCRIPTION
The 4 Meg 'NP' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
network and communications customers. They are
organized as 131,072 words by 32 bits, 131,072 words
by 36 bits and 262,144 words by 18 bits, fabricated with
ISSI
's advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable,
CKE
is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the
ADV input. When the ADV is HIGH the internal burst
counter is incremented. New external addresses can be
loaded when ADV is LOW.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when
WE
is LOW.
Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
FAST ACCESS TIME
Symbol
t
KQ
t
KC
Parameter
Clock Access Time
Cycle Time
Frequency
-150*
3.8
6.7
150
-133
4.2
7.5
133
-100
5
10
100
Units
ns
ns
MHz
*This speed available only in NP version
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
11/30/00
Rev. 00C
1
IS61NP12832
IS61NP12836
IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
PIN CONFIGURATION
119-pin PBGA (Top View) and 100-Pin TQFP
ISSI
A6
A7
CE
CE2
BWd
BWc
BWb
BWa
CE2
VCC
GND
CLK
WE
CKE
OE
ADV
NC
NC
A8
A9
®
1
A
VCCQ
B
NC
C
NC
D
DQc1
E
DQc2
F
VCCQ
G
DQc5
H
DQc7
J
VCCQ
K
DQd1
L
DQd4
M
VCCQ
N
DQd6
P
DQd8
R
NC
T
NC
U
VCCQ
2
3
4
5
6
7
A6
CE2
A7
NC
DQc3
DQc4
DQc6
DQc8
VCC
DQd2
DQd3
DQd5
DQd7
NC
A5
NC
NC
A4
A3
A2
GND
GND
GND
BWc
GND
NC
GND
BWd
GND
GND
GND
MODE
A10
NC
NC
ADV
VCC
NC
CE
OE
NC
WE
VCC
CLK
NC
CKE
A1
A0
VCC
A11
NC
A8
A9
A12
GND
GND
GND
BWb
GND
NC
GND
BWa
GND
GND
GND
VCC
A14
NC
A16
CE2
A15
NC
DQb6
DQb5
DQb4
DQb2
VCC
DQa7
DQa5
DQa4
DQa3
NC
A13
NC
NC
VCCQ
NC
NC
DQb8
DQb7
VCCQ
DQb3
DQb1
VCCQ
DQa8
DQa6
VCCQ
DQa2
DQa1
NC
ZZ
VCCQ
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
VCC
VCC
VCC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
VCC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
128K x 32
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Write Enable
Clock Enable
CE, CE2,
CE2 Synchronous Chip Enable
OE
DQa-DQd
MODE
V
CC
GND
V
CCQ
ZZ
Output Enable
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
Isolated Output Buffer Supply: +3.3V/2.5V
Snooze Enable
A2-A16
CLK
ADV
BWa-BWd
WE
CKE
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/30/00
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
3
IS61NP12832
IS61NP12836
IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
PIN CONFIGURATION
119-pin PBGA (Top View) and 100-Pin TQFP
ISSI
A6
A7
CE
CE2
BWd
BWc
BWb
BWa
CE2
VCC
GND
CLK
WE
CKE
OE
ADV
NC
NC
A8
A9
®
1
A
VCCQ
B
NC
C
NC
D
DQc1
E
DQc2
F
VCCQ
G
DQc5
H
DQc7
J
VCCQ
K
DQd1
L
DQd4
M
VCCQ
N
DQd6
P
DQd8
R
NC
T
NC
U
VCCQ
2
3
4
5
6
7
A6
CE2
A7
DQPc
DQc3
DQc4
DQc6
DQc8
VCC
DQd2
DQd3
DQd5
DQd7
DQPd
A5
NC
NC
A4
A3
A2
GND
GND
GND
BWc
GND
NC
GND
BWd
GND
GND
GND
MODE
A10
NC
NC
ADV
VCC
NC
CE
OE
NC
WE
VCC
CLK
NC
CKE
A1
A0
VCC
A11
NC
A8
A9
A12
GND
GND
GND
BWb
GND
NC
GND
BWa
GND
GND
GND
VCC
A14
NC
A16
CE2
A15
DQPb
DQb6
DQb5
DQb4
DQb2
VCC
DQa7
DQa5
DQa4
DQa3
DQPa
A13
NC
NC
VCCQ
NC
NC
DQb8
DQb7
VCCQ
DQb3
DQb1
VCCQ
DQa8
DQa6
VCCQ
DQa2
DQa1
NC
ZZ
VCCQ
DQPc
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
VCC
VCC
VCC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPb
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
VCC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
DQPa
128K x 36
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Write Enable
CKE
OE
DQa-DQd
MODE
V
CC
GND
V
CCQ
ZZ
DQPa-DQPd
Clock Enable
Output Enable
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
Isolated Output Buffer Supply: +3.3V/2.5V
Snooze Enable
Parity Data I/O
CE, CE2,
CE2 Synchronous Chip Enable
A2-A16
CLK
ADV
BWa-BWd
WE
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/30/00
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
IS61NP12832
IS61NP12836
IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
PIN CONFIGURATION
119-pin PBGA (Top View) and 100-Pin TQFP
ISSI
A6
A7
CE
CE2
NC
NC
BWb
BWa
CE2
VCC
GND
CLK
WE
CKE
OE
ADV
NC
NC
A8
A9
®
1
A
VCCQ
B
NC
C
NC
D
DQ9
E
NC
F
VCCQ
G
NC
H
DQ12
J
VCCQ
K
NC
L
DQ14
M
VCCQ
N
DQ16
P
NC
R
NC
T
NC
U
VCCQ
2
3
4
5
6
7
A6
CE2
A7
NC
DQ10
NC
DQ11
NC
VCC
DQ13
NC
DQ15
NC
DQP2
A5
A10
NC
A4
A3
A2
GND
GND
GND
BWb
GND
NC
GND
NC
GND
GND
GND
MODE
A11
NC
NC
ADV
VCC
NC
CE
OE
A17
WE
VCC
CLK
NC
CKE
A1
A0
VCC
NC
NC
A8
A9
A12
GND
GND
GND
NC
GND
NC
GND
BWa
GND
GND
GND
VCC
A14
NC
A16
CE2
A15
DQP1
NC
DQ7
NC
DQ5
VCC
NC
DQ3
NC
DQ2
NC
A13
NC
NC
VCCQ
NC
NC
NC
DQ8
VCCQ
DQ6
NC
VCCQ
DQ4
NC
VCCQ
NC
DQ1
NC
ZZ
VCCQ
NC
NC
NC
VCCQ
GND
NC
NC
DQ9
DQ10
GND
VCCQ
DQ11
DQ12
VCC
VCC
VCC
GND
DQ13
DQ14
VCCQ
GND
DQ15
DQ16
DQP2
NC
GND
VCCQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A10
NC
NC
VCCQ
GND
NC
DQP1
DQ8
DQ7
GND
VCCQ
DQ6
DQ5
GND
VCC
VCC
ZZ
DQ4
DQ3
VCCQ
GND
DQ2
DQ1
NC
NC
GND
VCCQ
NC
NC
NC
256K x 18
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Write Enable
Clock Enable
CE,
CE2,
CE2
Synchronous Chip Enable
OE
DQ1-DQ16
MODE
V
CC
GND
V
CCQ
ZZ
DQP1-DQP2
Output Enable
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
Isolated Output Buffer Supply: +3.3V/2.5V
Snooze Enable
Parity Data I/O DQP1 is parity for
DQ1-8; DQP2 is parity for DQ9-16
A2-A17
CLK
ADV
BWa-BWb
WE
CKE
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/30/00
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A11
A12
A13
A14
A15
A16
A17
5
京公网安备 11010802033920号
EEWORLD
