3D7205-20 datasheet, PDF - EEWORLD Datasheet

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3D7205-20: DescriptionSilicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDIP14, 0.300 INCH, DIP-14; Categorylogic logic; File Size42KB，4 Pages; ManufacturerData Delay Devices

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3D7205-20 Overview

Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDIP14, 0.300 INCH, DIP-14

3D7205-20 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	DIP
package instruction	0.300 INCH, DIP-14
Contacts	14
Reach Compliance Code	compliant
series	CMOS/TTL
Input frequency maximum value (fmax)	3.33 MHz
JESD-30 code	R-PDIP-T14
length	19.305 mm
Logic integrated circuit type	SILICON DELAY LINE
Number of functions	1
Number of taps/steps	5
Number of terminals	14
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
programmable delay line	NO
Certification status	Not Qualified
Maximum seat height	4.58 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Total delay nominal (td)	100 ns
width	7.62 mm
Base Number Matches	1

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3D7205

MONOLITHIC 5-TAP

FIXED DELAY LINE

(SERIES 3D7205)

FEATURES

•

1 8

VDD

All-silicon, low-power CMOS

2 7

technology

3 6

GND

4 5

TTL/CMOS compatible

inputs and outputs

3D7205Z

Vapor phase, IR and wave

SOIC

(150 Mil)

solderable

Auto-insertable (DIP pkg.)

Low ground bounce noise

Leading- and trailing-edge accuracy

Delay range:

8 through 500ns

Delay tolerance:

5% or 2ns

Temperature stability:

±3%

typical (0C-70C)

Vdd stability:

±2%

typical (4.75V-5.25V)

Minimum input pulse width:

20% of total delay

14-pin DIP and 16-pin SOIC available as drop-in

replacements for hybrid delay lines

data

delay

devices,

inc.

PACKAGES

GND

VDD

N/C

GND

VDD

N/C

3D7205M DIP

3D7205H Gull-Wing

(300 Mil)

N/C

GND

VDD

N/C

3D7205 DIP

3D7205G Gull-Wing

3D7205K Unused pins

removed

(300 Mil)

3D7205S SOIC

(300 Mil)

FUNCTIONAL DESCRIPTION

The 3D7205 5-Tap Delay Line product family consists of fixed-delay

CMOS integrated circuits. Each package contains a single delay line,

tapped and buffered at 5 points spaced uniformly in time. Tap-to-tap

(incremental) delay values can range from 8.0ns through 100ns. The

input is reproduced at the outputs without inversion, shifted in time as per

the user-specified dash number. The 3D7205 is TTL- and CMOS-

compatible, capable of driving ten 74LS-type loads, and features both

rising- and falling-edge accuracy.

PIN DESCRIPTIONS

VCC

GND

N/C

Delay Line Input

Tap 1 Output (20%)

Tap 2 Output (40%)

Tap 3 Output (60%)

Tap 4 Output (80%)

Tap 5 Output (100%)

+5 Volts

Ground

No Connection

The all-CMOS 3D7205 integrated circuit has been designed as a reliable,

economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 8-pin auto-insertable DIP

and a space saving surface mount 8-pin SOIC.

TABLE 1: PART NUMBER SPECIFICATIONS

PART NUMBER

DIP-8

3D7205M

3D7205H

SOIC-8

3D7205Z

DIP-14

3D7205

3D7205G

3D7205K

SOIC-16

3D7205S

TOLERANCES

TOTAL

DELAY (ns)

TAP-TAP

DELAY

(ns)

Max

Operating

Frequency

INPUT RESTRICTIONS

Absolute

Max

Oper. Freq.

Min

Operating

Pulse Width

Absolute

Min

Oper. P.W.

-8

-10

-15

-20

-25

-30

-50

-75

-100

NOTE:

-8

9.52 MHz

40.0

2.0

8.0

1.5

-10

6.67 MHz

50.0

2.5

10.0

2.0

-15

4.44 MHz

75.0

3.8

15.0

2.3

-20

3.33 MHz

100

5.0

20.0

2.5

-25

2.66 MHz

125

6.3

25.0

2.5

-30

2.22 MHz

150

7.5

30.0

3.0

-50

1.33 MHz

250

12.5

50.0

5.0

-75

0.89 MHz

375

18.8

75.0

7.5

-100

0.67 MHz

500

25.0 100

10.0

Any dash number between 8 and 100 not shown is also available.

71.4 MHz

50.0 MHz

33.3 MHz

25.0 MHz

20.0 MHz

16.7 MHz

10.0 MHz

6.67 MHz

5.00 MHz

52.5 ns

7.0 ns

75.0 ns

10.0 ns

113 ns

15.0 ns

150 ns

20.0 ns

188 ns

25.0 ns

225 ns

30.0 ns

375 ns

50.0 ns

563 ns

75.0 ns

750 ns

100.0 ns

1996 Data Delay Devices

Doc #96007

12/2/96

DATA DELAY DEVICES, INC.

3 Mt. Prospect Ave. Clifton, NJ 07013

3D7205-20 Related Products

	3D7205-20	3D7205-8
Description	Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDIP14, 0.300 INCH, DIP-14	Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDIP14, 0.300 INCH, DIP-14
Is it lead-free?	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible
Parts packaging code	DIP	DIP
package instruction	0.300 INCH, DIP-14	0.300 INCH, DIP-14
Contacts	14	14
Reach Compliance Code	compliant	compliant
series	CMOS/TTL	CMOS/TTL
Input frequency maximum value (fmax)	3.33 MHz	9.52 MHz
JESD-30 code	R-PDIP-T14	R-PDIP-T14
length	19.305 mm	19.305 mm
Logic integrated circuit type	SILICON DELAY LINE	SILICON DELAY LINE
Number of functions	1	1
Number of taps/steps	5	5
Number of terminals	14	14
Maximum operating temperature	70 °C	70 °C
Output polarity	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	DIP	DIP
Package shape	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
programmable delay line	NO	NO
Certification status	Not Qualified	Not Qualified
Maximum seat height	4.58 mm	4.58 mm
Maximum supply voltage (Vsup)	5.25 V	5.25 V
Minimum supply voltage (Vsup)	4.75 V	4.75 V
Nominal supply voltage (Vsup)	5 V	5 V
surface mount	NO	NO
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal form	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
Total delay nominal (td)	100 ns	40 ns
width	7.62 mm	7.62 mm

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