K9S1208V0M-SSB0 datasheet, PDF

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K9S1208V0M-SSB0: Description64M x 8 Bit SmartMedia Card; Categorystorage storage; File Size477KB，33 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K9S1208V0M-SSB0 Overview

64M x 8 Bit SmartMedia Card

K9S1208V0M-SSB0 Parametric

Parameter Name	Attribute value
Parts packaging code	CARD
package instruction	CARD-22
Contacts	22
Reach Compliance Code	unknow
ECCN code	3A991.B.1.A
Maximum access time	35 ns
Other features	CONTAINS ADDITIONAL 16M BIT NAND FLASH
JESD-30 code	R-XXMA-X22
memory density	536870912 bi
Memory IC Type	FLASH CARD
memory width	8
Number of functions	1
Number of terminals	22
word count	67108864 words
character code	64000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	55 °C
Minimum operating temperature
organize	64MX8
Package body material	UNSPECIFIED
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Parallel/Serial	PARALLEL
Programming voltage	2.7 V
Certification status	Not Qualified
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	UNSPECIFIED
Terminal location	UNSPECIFIED
type	NAND TYPE
Base Number Matches	1

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K9S1208V0M-SSB0

Document Title

64M x 8 Bit SmartMedia

Card

Revision History

Revision No

0.0

0.1

SmartMedia

History

Initial issue

1. Changed DC characteristics

Parameter

Operating

Current

Sequential Read

Program

Erase

Min

Typ

Max

20->30

Unit

Draft Date

Mar. 30th 2001

Apr. 7th 2001

Remark

preliminary

Final

2. Added t

DBSY

parameter 3. Removed Copy-Back program command

4. Changed AC characteristics

Parameter

ALE to RE Delay

( ID read )

Symbol

AR1

Min

100->10

Max

Unit

Note : For more detailed features and specifications including FAQ, please refer to Samsung’ Flash web site.

http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the

right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you

have any questions, please contact the SAMSUNG branch office near your office.

K9S1208V0M-SSB0

Product Introduction

SmartMedia

The K9S1208V0M is a 528Mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen col-

umns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating

data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of

16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the

32 pages formed by two NAND structures, totaling 8,192 NAND structures of 16 cells. The array organization is shown in Figure 2.

The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The mem-

ory array consists of 4,096 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the

K9S1208V0M.

The K9S1208V0M has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems

upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through

I/O's by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address

Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. The 64M byte physical space requires

26 addresses, thereby requiring four cycles for byte-level addressing: column address, low row address and high row address, in that

order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase

operation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into

the command register. Table 1 defines the specific commands of the K9S1208V0M.

The device provides simultaneous program/erase capability up to four pages/blocks. By dividing the memory array into four 128Mbit

separate planes, simultaneous multi-plane operation dramatically increases program/erase performance by 4X while still maintaining

the conventional 512 byte structure.

The extended pass/fail status for multi-plane program/erase allows system software to quickly identify the failing page/block out of

selected multiple pages/blocks. Usage of multi-plane operations will be described further throughout this document.

Table 1. Command Sets

Function

Read ID (1)

Read ID (2)

Reset

Page Program (True)

Page Program (Dummy)

Page Program (Multi Block Program)

Block Erase

Multi-Plane Block Erase

Read Status

Read Multi-Plane Status

1st. Cycle

00h/01h

(1)

50h

90h

91h

FFh

80h

60h

60h---60h

70h

71h

(2)

2nd. Cycle

10h

11h

15h

D0h

3rd. Cycle

Acceptable Command

NOTE

: 1. The 00h command defines starting address of the 1st half of registers.

The 01h command defines starting address of the 2nd half of registers.

After data access on the 2nd half of register by the 01h command, the status pointer is

automatically moved to the 1st half register(00h) on the next cycle.

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