CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
DC Electrical Specifications
T
A
= 25°C, V+ = 15, V- = -10V, B+ = V
CH
+3.6V, B- = V
CL
-3.6V, No Load. Data and OE levels are:
L = 2.0V and H = 3.0V (CMOS thresholds). E levels are: L = 1.5V and H = 3.5V. All tests done using
2N2222 and 2N2907 output transistors with Beta>40 @ I
C
= 400mA and Beta>27 @ I
C
= 500mA and
V
CE
= 3.1V. OE and E low.
PARAMETER
I
S
DESCRIPTION
V+, -Supply Currents
CONDITIONS
V
CH
= 5V, V
CL
= 0, VSR = 2.5V, Data = H or L
V
CH
= 11V, V
CL
= -6V, VSR = 5V, Data = H or L
V
CH
= -6V, V
CL
= 11V, VSR+2.5V, Data = H or L
V
CH
= 5V, V
CL
= 0V, VSR = 2.5V, Data = H or L, E = H
V
CH
= -1V to +7.5V, V
CL
= 0V, VSR = 5V,
Data = H or L
V
CL
= -3.5V to +3.5V, V
CH
= 0V, VSR = 5V,
Data = H or L
V
CH
= 5V, V
CL
= 0V, VSR = 5V, Data = 0 or 5V
V
CH
= 5V, V
CL
= 0V, VSR = 5V, Data = L, OE = 0V or 5V
V
CH
= 5V, V
CL
= 0V, VSR = 5V, Data = L, E = 0V or 5V
V
CH
= 5V, V
CL
= 0V, Data = L, VSR = 0V or 5V
V
CH
= 5V, V
CL
= 0V, VSR = 5V, Data = 0V or 5V
V
CH
= 5V, V
CL
= 0V, Data = L, VSR = 5V
V+ = 14.5V, V- = -9.5V
V
CH
= 5V, V
CL
= 0, VSR = 1V, Data = L,
Output Current = -100mA, 0mA, or +100mA
Output Current = -400mA or +400mA
Output Current = -500mA or +500mA
V
CH
= 5V, V
CL
= 0, VSR = 1V, Data = H
Output Current = -100mA, 0mA, or +100mA
Output Current = -400mA or +400mA
Output Current = -500mA or +500mA
V
CH
= 11V, V
CL
= -6V, VSR = 1V, I
OUT
= 0, Data = L
V
CH
= 11V, V
CL
= -6V, VSR = 1V, I
OUT
= 0, Data = H
V
CH
= 5V, V
CL
= 0, VSR = 2.5V, R
SENSE
= 1Ω, Data = H
V
CH
= 5V, V
CL
= 0, VSR = 2.5V, R
SENSE
= 1Ω, Data = L
V
CH
= 5V, V
CL
= 0, VSR = 2.5V, Data L or H,
Output Current = -350mA or +350mA
Output Current = -550mA or +550mA
V
CH
= 5V, V
CL
= 0, VSR = 2.5V, Data = L, OE = H,
Output Voltage = -2.5V or +7.5V
MIN
15
21
15
0
-20
-20
-50
-20
-20
-20
-20
-20
TYP
25
33
25
0.5
5
-5
5
5
2
2
5
5
MAX
30
45
30
2.5
20
20
50
20
20
20
20
20
UNITS
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
I
S
, disabled
I
VCH
I
VCL
I
DATA
I
OE
I
E
I
VSR
±I
SENSE
I
B
+, I
B
-
V
O
V+, -Supply Currents
V
CH
Input Current
V
CL
Input Current
Data Input Current
OE Input Current
E Input Current
VSR Input Current
Sense Input Currents
B+, B- Input Currents
Output Voltage
-50
-300
-600
4.95
4.7
4.4
-6.1
10.9
400
-400
0
3.5
-100
5
450
-450
50
300
600
5.05
5.3
5.6
-5.9
11.1
600
-600
0.6
5.0
100
mV
mV
mV
V
V
V
V
V
mA
mA
V
V
µA
I
SENSE+
I
SENSE-
V
O, SENSE
+ISENSE
Threshold
-ISENSE
Threshold
Sense Out Levels
I
OUT,TRI
High-Impedance
Output Leakage
2
EL2021
AC Electrical Specifications
PARAMETER
SR+
SR-
SRSYM
T
PD
T
S
OS
DESCRIPTION
+Slew Rate
-Slew Rate
Slew Rate
Symmetry
Propagation Delay
Settling Time
Overshoot
DC test conditions apply except where noted. For AC tests, R
L
= 1k, C
L
= 200pF. Delay times are
measured from OE or Data crossing 2.5V, V
CH
= 5V, V
CL
= 0.
CONDITIONS
Data L to H, Output from 0.5V to 4.5V, VSR = 1V
VSR = 3V
Data H to L, Output from 4.5V to 0.5V, VSR = 1V
VSR = 3V
(
SR+
)- (
SR-
)
VSR
=
1V
-------------------------------------
-
(
SR+
)+ (
SR-
)
VSR
=
2V
Data L to H, Output to 0.2V, VSR = 2.5V
Data H to L, Output to 4.8V, VSR = 2.5V
VSR = 5V, Data L to H, Output 4.5V to 5V±0.2V
VSR = 5V, Data H to L, Output 0.5V to ±0.2V
VSR = 1V, Data L to H or H to L
VSR = 1V, OE H to L, Data = L, R
L
to 5V
VSR = 1V, OE H to L, Data = H, R
L
to 0V
VSR = 2.5V, OE H to L, C
L
= 50pF
R
L
to 5V, Data = L, Output to 3.5V
R
L
to 0V, Data = H, Output to 1.5V
VSR = 2.5V, OE L to H, C
L
= 50pF,
Data = L, R
L
to 5V, Output to 0.5V
Data = H, R
L
to 0V, Output to 4.5V
-300
-300
-300
MIN
80
150
-80
-150
-10
-20
6.5
6.5
9
9
TYP
100
240
-100
-240
MAX
120
360
-120
-360
10
20
11.5
11.5
30
30
300
300
300
50
50
50
50
UNITS
V/µs
V/µs
V/µs
V/µs
%
%
ns
ns
ns
ns
mV
mV
mV
ns
ns
ns
ns
T
PDA
Propagation Delay,
High-Z to Active
Propagation Delay,
Active to High-Z
T
PDH
Pin Description Table
PIN #
1
2
GND
E
NAME
System ground.
Enable control input. A logic low allows normal operation; a logic high puts the device into
power down mode. No output levels are defined in powerdown nor does the output behave
as a high impedance.
Output Enable input. A logic low sets the output to low-impedance driver mode; a logic high
places the output into a high-impedance state.
Lower analog control input. When Data = OE = E = L, the V
CL
level is output as V
OUT
(assuming V
CL
< V
CH
).
System power supply. The EL2021 uses this pin as a negative output current monitor connection.
Little current is drawn from this pin, transient or static.
Negative output current monitor input.
Negative power supply. Because all negative output drive currents come from this pin
(as much as 60mA transiently), good bypassing is essential.
Output to external pnp transistor base.
High-current input and output, depending on OE.
Output to external npn transistor base.
Logic output which signals that a high + or - output current is flowing.
Positive power supply. Like V-, it should be well bypassed.
Positive output current monitor input.
System power supply, similar to B-.
Higher analog control input. When Data = H and OE = E = L, the V
CH
level is output as
V
OUT
(assuming V
CH
> V
CL
).
Slew rate control input. A 1V level on this pin causes the output to slew at 100V/µs, 0.5V
causes a slew rate of 50V/µs, etc.
Output level control input. This pin digitally selects V
CL
or V
CH
as the output voltage
when OE = E = L.
Not Connected.
DESCRIPTION
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
OE
V
CL
B-
I
SENSE
-
V-
Drive-
V
OUT
Drive+
Sense Out
V+
I
SENSE
+
B+
V
CH
VSR
Data
N/C
3
EL2021
Typical Performance Curves
Family of output waveshapes.
ECL, TTL, CMOS, HCMOS
with C1 = 50pF, VSR = 1V.
Family of output waveshapes.
ECL, TTL, CMOS, HCMOS
with C1 = 200pF, VSR = 1V.
erting Gains
Output waveshapes with
5 MHz data rate. C1 = 50pF,
VSR = 4V.
Family of output waveshapes.
ECL, TTL, CMOS, HCMOS
with C1 = 200pF, VSR = 1V,
and overcompensated with
22pF from each drive pin
to ground.
Family of output waveshapes
from active H, L to
high-impedance H, L.
Family of output waveshapes
from high-impedance H, L
to active H, L.
Family of + output edges,
0V to 5V for VSR = 0.5V, 1V,
2V, 3V, 5V.
Family of—output edges,
5V to 0V or VSR = 0.5V, 1V,
2V, 3V, 5V.
4
EL2021
Typical Performance Curves
(Continued)
Overshoot vs VSR
Overshoot vs VSR
Slew Rate vs VSR
V
OUT
vs Load Current
Supply Current vs
Supply Voltage
Tri-State Leakage vs
Output Voltage
Supply Current vs VSR
Power Dissipation vs
Temperature
Applications Information
Output Stage
To meet the requirements of low output impedance, wide
bandwidth, and large capacitive load driving capability, the
EL2021 has a fairly exotic output stage. Figure 1 shows a
simplified schematic of the circuit, only applicable in normal,
low impedance mode. External transistors are used to
handle the large load currents and peak power dissipations.
Since there is no need for good AC crossover distortion
performance in a pin driver, the output transistors are
operated class C. That is, for small output currents, neither
output transistor will conduct bias current, and when load
currents do flow, one of the devices is off. This is
accomplished by biasing the output transistors from Schottky
diodes D1 and D2. In operation, the diode forward voltage is
about 0.4V, whereas the “on” output transistor will have a
V
BE
of 0.6V. This leaves only 0.2V across the “off”
transistor's base-emitter junction, not nearly enough to
cause bias currents to flow in it. Schottky diodes have a
temperature drift similar to silicon transistors, so the class C
bias maintains over temperature. One caution is that the
diodes are in the IC package and are thermally separate
from the transistors, so there can exist temperature
differences between packages that can cause thermal
runaway. Runaway is avoided as long as the external
transistors are not hotter than the EL2021 package by more
than 80°C. The only way runaway has been induced as of
this writing is to use “freeze spray” on the IC package while
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