NG80960JF-33 datasheet, PDF - EEWORLD Datasheet

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NG80960JF-33: Description32-BIT, 100 MHz, RISC PROCESSOR, PQFP132; CategoryThe embedded processor and controller Microcontrollers and processors; File Size642KB，77 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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NG80960JF-33 Overview

32-BIT, 100 MHz, RISC PROCESSOR, PQFP132

NG80960JF-33 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	QFP
package instruction	BQFP, SPQFP132,1.1SQ
Contacts	132
Reach Compliance Code	unknow
ECCN code	3A991.A.2
Is Samacsys	N
Other features	OPERATING CASE TEMPERATURE 0 TO 100 C
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	33.3 MHz
External data bus width	32
Format	FIXED POINT
Integrated cache	YES
JESD-30 code	S-PQFP-G132
JESD-609 code	e0
length	24.13 mm
low power mode	YES
Number of terminals	132
Package body material	PLASTIC/EPOXY
encapsulated code	BQFP
Encapsulate equivalent code	SPQFP132,1.1SQ
Package shape	SQUARE
Package form	FLATPACK, BUMPER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3,3.3/5 V
Certification status	Not Qualified
Maximum seat height	4.57 mm
speed	33 MHz
Maximum slew rate	320 mA
Maximum supply voltage	3.45 V
Minimum supply voltage	3.15 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	24.13 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC
Base Number Matches	1

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80960JA/JF/JD/JT 3.3 V EMBEDDED

32-BIT MICROPROCESSOR

Advance Information Datasheet

Product Features

Pin/Code Compatible with all 80960Jx

Processors

High-Performance Embedded Architecture

—One Instruction/Clock Execution

—Core Clock Rate is:

80960JA/JF 1x the Bus Clock

80960JD 2x the Bus Clock

80960JT 3x the Bus Clock

—Load/Store Programming Model

—Sixteen 32-Bit Global Registers

—Sixteen 32-Bit Local Registers (8 sets)

—Nine Addressing Modes

—User/Supervisor Protection Model

Two-Way Set Associative Instruction

Cache

—80960JA - 2 Kbyte

—80960JF/JD - 4 Kbyte

—80960JT - 16 Kbyte

—Programmable Cache-Locking

Mechanism

Direct Mapped Data Cache

—80960JA - 1 Kbyte

—80960JF/JD - 2 Kbyte

—80960JT - 4 Kbyte

—Write Through Operation

On-Chip Stack Frame Cache

—Seven Register Sets Can Be Saved

—Automatic Allocation on Call/Return

—0-7 Frames Reserved for High-Priority

Interrupts

On-Chip Data RAM

—1 Kbyte Critical Variable Storage

—Single-Cycle Access

3.3 V Supply Voltage

—5 V Tolerant Inputs

—TTL Compatible Outputs

High Bandwidth Burst Bus

—32-Bit Multiplexed Address/Data

—Programmable Memory Configuration

—Selectable 8-, 16-, 32-Bit Bus Widths

—Supports Unaligned Accesses

—Big or Little Endian Byte Ordering

High-Speed Interrupt Controller

—31 Programmable Priorities

—Eight Maskable Pins plus NMI

—Up to 240 Vectors in Expanded Mode

Two On-Chip Timers

—Independent 32-Bit Counting

—Clock Prescaling by 1, 2, 4 or 8

—lnternal Interrupt Sources

Halt Mode for Low Power

IEEE 1149.1 (JTAG) Boundary Scan

Compatibility

Packages

—132-Lead Pin Grid Array (PGA)

—132-Lead Plastic Quad Flat Pack

(PQFP)

—196-Ball Mini Plastic Ball Grid Array

(MPBGA)

Notice:

This document contains information on products in the sampling and initial production

phases of development. The specifications are subject to change without notice. Verify with your

local Intel sales office that you have the latest datasheet before finalizing a design.

Order Number: 273159-001

March, 1998

80960JA/JF/JD/JT 3.3 V Microprocessor

Contents

1.0

2.0

Introduction

.................................................................................................................. 7

80960Jx Overview

...................................................................................................... 7

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

80960 Processor Core .......................................................................................... 9

Burst Bus.............................................................................................................10

Timer Unit............................................................................................................10

Priority Interrupt Controller ..................................................................................10

Instruction Set Summary .....................................................................................11

Faults and Debugging .........................................................................................11

Low Power Operation..........................................................................................11

Test Features ......................................................................................................12

Memory-Mapped Control Registers ....................................................................12

Data Types and Memory Addressing Modes ......................................................12

Pin Descriptions ..................................................................................................16

3.1.1 Functional Pin Definitions.......................................................................16

3.1.2 80960Jx 132-Lead PGA Pinout..............................................................22

3.1.3 80960Jx 132-Lead PQFP Pinout............................................................26

3.1.4 80960Jx 196-Ball MPBGA Pinout ..........................................................29

Package Thermal Specifications .........................................................................34

Thermal Management Accessories.....................................................................38

3.3.1 Heatsinks................................................................................................38

Absolute Maximum Ratings.................................................................................39

Operating Conditions...........................................................................................39

Connection Recommendations ...........................................................................40

VCC5 Pin Requirements (VDIFF) .......................................................................40

VCCPLL Pin Requirements.................................................................................41

DC Specifications ................................................................................................42

AC Specifications ................................................................................................44

4.7.1 AC Test Conditions and Derating Curves ..............................................47

4.7.2 AC Timing Waveforms ...........................................................................52

Basic Bus States .................................................................................................68

Boundary-Scan Register .....................................................................................69

3.0

Package Information

...............................................................................................14

3.1

3.2

3.3

4.0

Electrical Specifications

........................................................................................39

4.1

4.2

4.3

4.4

4.5

4.6

4.7

5.0

Bus Functional Waveforms

..................................................................................58

5.1

5.2

6.0

7.0

Device Identification

...............................................................................................74

Revision History

.......................................................................................................77

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

Figures

80960Jx Microprocessor Package Options...........................................................7

80960Jx Block Diagram ........................................................................................9

132-Lead Pin Grid Array Bottom View - Pins Facing Up.....................................22

132-Lead Pin Grid Array Top View - Pins Facing Down .....................................23

132-Lead PQFP - Top View ................................................................................26

196-Ball Mini Plastic Ball Grid Array Bottom View - Balls Facing Up ..................29

196-Ball Mini Plastic Ball Grid Array Top View - Balls Facing Down ..................30

VCC5 Current-Limiting Resistor ..........................................................................40

VCCPLL Lowpass Filter ......................................................................................41

AC Test Load ......................................................................................................47

Output Delay or Hold vs. Load Capacitance .......................................................48

vs. AD Bus Load Capacitance......................................................................48

80960JA/JF I

Active (Power Supply) vs. Frequency .......................................49

80960JA/JF I

Active (Thermal) vs. Frequency ................................................49

80960JD I

Active (Power Supply) vs. Frequency............................................50

80960JD I

Active (Thermal) vs. Frequency.....................................................50

80960JT I

Active (Power Supply) vs. Frequency ...........................................51

80960JT I

Active (Thermal) vs. Frequency .....................................................51

CLKIN Waveform ................................................................................................52

OV1

Output Delay Waveform .............................................................................52

Output Float Waveform................................................................................53

IS1

and T

IH1

Input Setup and Hold Waveform ...................................................53

IS2

and T

IH2

Input Setup and Hold Waveform ...................................................53

IS3

and T

IH3

Input Setup and Hold Waveform ...................................................54

IS4

and T

IH4

Input Setup and Hold Waveform ...................................................54

, T

LXL

and T

LXA

Relative Timings Waveform.................................................55

DT/R and DEN Timings Waveform .....................................................................55

TCK Waveform....................................................................................................56

BSIS1

and T

BSIH1

Input Setup and Hold Waveforms .........................................56

BSOV1

and T

BSOF1

Output Delay and Output Float Waveform..........................56

BSOV2

and T

BSOF2

Output Delay and Output Float Waveform..........................57

BSIS2

and T

BSIH2

Input Setup and Hold Waveform ...........................................57

Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus .........58

Burst Read and Write Transactions Without Wait States, 32-Bit Bus .................59

Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus...........................60

Burst Read and Write Transactions Without Wait States, 8-Bit Bus ...................61

Burst Read and Write Transactions With 1, 0 Wait States and

Extra Tr State on Read, 16-Bit Bus .....................................................................62

Double Word Read Bus Request, Misaligned One Byte From

Quad Word Boundary, 32-Bit Bus, Little Endian .................................................63

HOLD/HOLDA Waveform For Bus Arbitration ....................................................64

Cold Reset Waveform .........................................................................................65

Warm Reset Waveform .......................................................................................66

Entering the ONCE State ....................................................................................67

Bus States with Arbitration ..................................................................................68

Summary of Aligned and Unaligned Accesses (32-Bit Bus) ...............................72

Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) ...........73

80960JT Device Identification Register...............................................................74

80960JD Device Identification Register ..............................................................75

80960JA/JF Device Identification Register .........................................................76

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

Tables

80960Jx Instruction Set.......................................................................................13

Pin Description Nomenclature.............................................................................16

Pin Description — External Bus Signals .............................................................17

Pin Description — Processor Control Signals, Test Signals and Power .............20

Pin Description — Interrupt Unit Signals .............................................................21

132-Lead PGA Pinout — In Signal Order............................................................24

132-Lead PGA Pinout — In Pin Order ................................................................25

132-Lead PQFP Pinout — In Signal Order .........................................................27

132-Lead PQFP Pinout — In Pin Order ..............................................................28

196-Ball MPBGA Pinout — In Signal Order ........................................................31

196-Ball MPBGA Pinout — In Pin Order .............................................................33

132-Lead PGA Package Thermal Characteristics...............................................35

196-Ball MPBGA Package Thermal Characteristics ...........................................35

132-Lead PQFP Package Thermal Characteristics ............................................36

Maximum T

at Various Airflows in °C (80960JT) ...............................................36

Maximum T

at Various Airflows in °C (80960JD) ..............................................37

Maximum T

at Various Airflows in °C (80960JA/JF)..........................................37

Absolute Maximum Ratings.................................................................................39

80960Jx Operating Conditions ............................................................................39

VDIFF Parameters ..............................................................................................40

80960Jx DC Characteristics................................................................................42

80960Jx I

Characteristics................................................................................42

80960Jx AC Characteristics ................................................................................44

Note Definitions for Table 23, 80960Jx AC Characteristics (pg. 44) ...................47

Boundary-Scan Register Bit Order......................................................................69

Natural Boundaries for Load and Store Accesses ..............................................70

Summary of Byte Load and Store Accesses.......................................................70

Summary of Short Word Load and Store Accesses............................................70

Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4)...........................71

80960Jx Device Type and Stepping Reference ..................................................74

Fields of 80960JT Device ID ...............................................................................75

80960JT Device ID Model Types ........................................................................75

Fields of 80960JD Device ID...............................................................................76

80960JD Device ID Model Types........................................................................76

Fields of 80960JA/JF Device ID ..........................................................................77

80960JA/JF Device ID Model Types ...................................................................77

Data Sheet Revision History ...............................................................................77

Advance Information Datasheet

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